Adaptive Erase Time Compensation for Segmented Memory Erase
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in efficiently managing erase operations, particularly in suspended and resumed states, which can lead to issues such as over-erasure and reduced reliability due to inadequate control over the erase process.
Innovation Solution
A memory apparatus and method that involve a control circuit adjusting the erase time period and applying a segmented erase signal with multiple voltage segments to optimize the erase operation, allowing for resumed operations without significant latency or reliability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a segmented erase operation is suspended and resumed, then the memory device can handle higher priority operations, but the erase time period becomes uncontrolled leading to over-erasure and reliability issues
Solution Approach 1:
The patent applies dynamics by making the erase time period adjustable and adaptive. The control circuit dynamically modifies the erase time period based on whether the operation is initial or resumed, allowing the system to adapt to different operational states while maintaining reliability control
Solution Approach 2:
The patent implements feedback by having the control circuit track and monitor the segmented erase operation state. The control circuit uses this feedback information to determine whether to apply the first or second erase time period, ensuring proper control throughout the suspended and resumed operation cycles
2Reliability
If the erase time period is extended to accommodate suspended and resumed operations, then reliability is maintained, but the erase operation takes longer completing
Solution Approach 1:
The patent applies parameter changes by modifying the erase time period parameter based on the operational state. The control circuit switches between a first erase time period for initial operations and a second, longer erase time period for resumed operations, optimizing the balance between reliability and time efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise control over the erase process, reducing over-erasure and improving the reliability and efficiency of memory cell erasure operations, even when operations are suspended and resumed, by elongating the ramping time portion and adjusting the quantity of voltage segments.
Implementation Method 1
Erasing the memory cells can be achieved by removing the electrons from the floating gate or charge trapping layer, thereby lowering the threshold voltage
Implementation Method 2
simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines
Data Source
AI summary
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.