Adaptive SerDes CDR Clock Division for Lower Receiver Power
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Solution Overview
Problem
Conventional serializer-deserializer (SerDes) systems face challenges in reducing power consumption, particularly in clock data recovery (CDR) circuits, which are difficult to implement effectively without on-chip thermal sensors and require frequent activation, leading to inefficiencies in high-speed communication.
Innovation Solution
A CDR circuit that filters phase differences between a sampling clock signal and a received serial data stream, using a mixer to phase align the clock signal, a clock divider to reduce frequency after lock is achieved, and a phase detector to determine phase alignment, thereby reducing power consumption by increasing the divisor value once synchronization is established.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the CDR circuit is periodically disabled to save power, then power consumption is reduced, but the circuit cannot maintain continuous clock alignment with the data stream
Solution Approach 1:
The CDR circuit is periodically disabled by controlling the phase detector to operate only during specific intervals (e.g., every Nth data period or during designated sampling windows). This periodic operation reduces power consumption while maintaining functional capability, as the circuit re-synchronizes periodically rather than continuously.
Solution Approach 2:
The system dynamically adjusts the operating state of the CDR circuit based on operational needs. The phase detector transitions between active and inactive states, and the divisor value is dynamically changed between a first value (when active) and a second value (when inactive), allowing the circuit to adapt its power consumption to actual synchronization requirements.
2Reliability
If the CDR circuit operates continuously to maintain clock alignment, then clock synchronization is maintained, but power consumption increases
Solution Approach 1:
The CDR circuit is periodically disabled by controlling the phase detector to operate only during specific intervals (e.g., every Nth data period or during designated sampling windows). This periodic operation reduces power consumption while maintaining functional capability, as the circuit re-synchronizes periodically rather than continuously.
Solution Approach 2:
The system dynamically adjusts the operating state of the CDR circuit based on operational needs. The phase detector transitions between active and inactive states, and the divisor value is dynamically changed between a first value (when active) and a second value (when inactive), allowing the circuit to adapt its power consumption to actual synchronization requirements.
3Use of energy by moving object
If the divisor value is increased to reduce power consumption, then the divided clock frequency is reduced and power is saved, but the phase detection accuracy may be compromised
Solution Approach 1:
The divisor value is dynamically adjusted between a first value and a second value based on the operational state of the CDR circuit. When the phase detector is active, a first divisor value is used; when inactive, a second divisor value is used. This dynamic adjustment allows the system to optimize power consumption while maintaining phase detection capability when needed.
Solution Approach 2:
The system changes the divisor parameter of the clock divider based on operational requirements. By switching between different divisor values, the system can reduce the divided clock frequency (and thus power consumption) when continuous phase detection is not required, while maintaining higher frequency accuracy when synchronization is critical.
Data Source
AI summary
A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.