Adaptive Shared Cache Management Using Inactive Core Private Caches
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Solution Overview
Problem
Multi-core processors face performance degradation due to cache capacity constraints, leading to increased memory access times and bandwidth usage, as limited shared cache capacity necessitates evicting cache lines, which then need to be retrieved again, causing inefficiencies.
Innovation Solution
The implementation of adaptive shared cache management, where inactive processing elements' private caches are repurposed as extended Last Level Cache (LLC) storage, allowing for dynamic adjustment of shared cache size without adding hardware or sacrificing performance, by identifying and relocating victim cache lines to inactive cores' private caches instead of main memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shared cache capacity is increased, then cache hit rate is improved, but hardware cost and device complexity increase
Solution Approach 1:
The private caches of inactive processing elements are repurposed to serve as extended shared cache storage. When a processing element is inactive, its private cache can be allocated to store cache lines for other active processing elements, making the cache resource universally accessible across different operational states.
Solution Approach 2:
The system dynamically changes the effective cache capacity parameter by allocating private cache spaces of inactive processing elements to the shared cache pool. This allows the shared cache size to adapt based on the number of active processing elements without physical hardware changes.
2Loss of time
If shared cache capacity is increased, then memory access time is reduced, but hardware cost increases
Solution Approach 1:
Private caches serve dual purposes: storing data for their owning processing element when active, and serving as extended shared cache storage when inactive, thereby reducing memory access time for active elements without additional hardware.
Solution Approach 2:
Inactive processing elements' private caches automatically become available to serve the shared cache needs of active elements, providing a self-service mechanism where idle resources contribute to system performance without external intervention.
3Quantity of substance
If private caches of inactive processing elements are used as extended shared cache, then shared cache capacity is increased, but cache management complexity increases
Solution Approach 1:
The cache controller continuously monitors the operational state of processing elements and dynamically adjusts cache line allocation between private and shared cache spaces based on this feedback, optimizing cache capacity without manual intervention.
Solution Approach 2:
The cache allocation is dynamic rather than static, allowing the boundary between private and shared cache spaces to shift based on the real-time operational state of processing elements, maximizing shared cache capacity when elements are inactive.
4Loss of energy
If cache lines are evicted to inactive processing elements' private caches, then memory bandwidth usage is reduced, but system complexity increases
Solution Approach 1:
Inactive processing elements' private caches act as intermediary storage between the shared cache and main memory, capturing evicted cache lines that would otherwise require main memory access, thereby reducing memory bandwidth usage.
Solution Approach 2:
The system proactively identifies and captures cache lines for eviction to inactive processing elements' private caches before they would be written to main memory, preventing unnecessary memory traffic in advance.
Data Source
AI summary
Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.