Adaptive SIFT Descriptor Generation for FPGA Memory Optimization
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Solution Overview
Problem
The scale-invariant feature transform (SIFT) algorithm requires excessive memory for descriptor storage, even when implemented on platforms like FPGA, due to its high computational demands and memory usage, which is not efficiently managed, especially when compared to simpler algorithms like ORB.
Innovation Solution
A method is introduced to dynamically adjust the size of sub-patches and the number of bins in the SIFT algorithm based on available memory resources, allowing for adaptive memory allocation and reduced memory usage by determining the number of bits allocated to each bin, thereby optimizing memory management for descriptor generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SIFT algorithm is used to generate descriptors, then the robustness against environmental conditions (lens distortion, angle, lighting) is improved, but the memory usage for storing descriptors increases significantly compared to the ORB algorithm
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the descriptor dimension (e.g., changing from 128 to 64 or 32 dimensions) and the number of feature points extracted based on available memory resources. This allows the system to maintain SIFT's robustness while adapting the memory footprint to match embedded system constraints, directly resolving the contradiction between reliability and memory usage.
2Measurement precision
If the SIFT algorithm is implemented with elaborate descriptor configuration, then the accuracy of feature point representation is improved, but the computation speed decreases due to high computational demands
Solution Approach 1:
The patent implements dynamics by making the descriptor generation process adaptive rather than static. The system dynamically adjusts descriptor dimensions and feature point selection based on real-time memory availability and computational constraints, allowing it to maintain high accuracy when resources permit while reducing computation speed requirements when resources are limited.
3Productivity
If the SIFT algorithm is implemented on an FPGA platform, then the real-time processing capability is improved, but the memory usage remains four times higher than the ORB algorithm
Solution Approach 1:
The patent applies parameter changes specifically for FPGA implementation by optimizing descriptor dimensions and feature point counts to achieve real-time processing while dramatically reducing memory usage. By adjusting these parameters, the system achieves both real-time capability and reduced memory footprint compared to traditional SIFT implementation on the same platform.
Data Source
AI summary
The present invention, according to one embodiment, in order to generate a descriptor for a feature point extracted from an input image, may: determine the size of each of a plurality of sub-patches included in a main patch having a preset size on the basis of the feature point in the input image; calculate gradient directions for each pixel constituting a target sub-patch from among the plurality of sub-patches; determine the number of bins for distinguishing the gradient directions; generate, with respect to the target sub-patch, a histogram for a plurality of bins on the basis of the gradient directions of the pixels constituting the target sub-patch; and generate a descriptor for the feature point on the basis of the histogram. Various other embodiments may also be possible.