Adaptive Signal Synchronizer Using Programmable Delay Elements
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Solution Overview
Problem
Existing signal synchronizers for multiple clock domains often fail to accurately synchronize signals, leading to meta-stable states and incorrect data transmission due to differences in clock signal periods, resulting in missed or partially registered pulses in the destination clock domain.
Innovation Solution
A synchronizer that includes a first unit for receiving inputs indicating source and destination clock periods and a communication signal, which stretches the signal according to the destination clock period to ensure it meets setup and hold time requirements in the destination clock domain, using a pulse stretching block and cascaded synchronizer to adaptively instantiate registers and delay elements for flexible operation across multiple clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional synchronizer using cascaded flip-flops is used, then the signal is synchronized between clock domains, but the synchronizer fails to accurately register pulses when clock periods differ significantly, leading to meta-stable states and data loss
Solution Approach 1:
The patent changes the fundamental parameter of the synchronizer from using fixed clock-period flip-flops to using programmable delay elements with adjustable delay values. The delay elements can be configured to match the specific clock period differences between source and destination domains, enabling accurate pulse registration without meta-stable states. This parameter adjustment allows the synchronizer to adapt to various clock domain scenarios.
Solution Approach 2:
The synchronizer employs dynamically adjustable delay elements that can be reconfigured based on the specific clock domain parameters. Rather than using fixed cascaded flip-flops, the system uses delay elements whose delay values can be programmed to match the actual clock period differences, making the synchronizer adaptive and dynamic rather than static.
2Reliability
If the number of cascaded flip-flops in the synchronizer is increased, then the probability of meta-stable state decreases, but the device complexity and propagation delay increase
Solution Approach 1:
Instead of increasing the number of cascaded stages, the patent changes the approach by using programmable delay elements that can be configured with specific delay values matching the clock period differences. This single-stage configurable delay approach achieves meta-stability suppression without the cumulative propagation delay that would result from cascading multiple fixed delay flip-flops.
3Ease of manufacture
If a fixed structure synchronizer is used, then the design is simple, but it cannot adapt to different clock period relationships between source and destination domains
Solution Approach 1:
The synchronizer uses programmable delay elements that can be reconfigured to adapt to different clock period relationships between source and destination domains. The delay values can be programmed based on the specific clock domain parameters, providing versatility while maintaining a relatively simple single-stage structure compared to multiple cascaded stages.
Solution Approach 2:
The synchronizer design uses universal programmable delay elements that can function across multiple clock domain scenarios. Rather than designing different synchronizers for different clock period relationships, a single programmable structure can be configured to handle various clock domain combinations, making the design universally applicable.
Data Source
AI summary
A synchronizer and a method for synchronizing a communication signal are presented. The synchronizer comprises a first unit arranged for receiving a plurality of inputs. The plurality of inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal. The first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period. The synchronizer is further provided with a second unit. The second unit is configured for operating according to the indicative of destination clock period. The output of the first unit is provided to the second unit. The second unit is configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.