Adaptive Single-Side Erase for Memory Cell Reliability
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Solution Overview
Problem
Existing memory devices face challenges in efficiently erasing memory cells, particularly due to variations in erase speeds among different memory strings, which can lead to degradation of memory cell reliability and data retention.
Innovation Solution
The memory device employs a control circuitry that performs an erase operation by supplying a first erase voltage pulse, followed by bias voltages with different magnitudes to inhibit the second erase voltage pulse in selected memory strings, thereby optimizing the erase process based on the number of memory cells that did not pass the erase verify operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform erase voltage pulse is applied to all memory strings, then the erase operation can be simplified, but memory cell reliability degrades due to variations in erase speeds among different memory strings
Solution Approach 1:
The patent applies different bias voltages to different memory strings based on their individual erase performance. Memory strings are categorized into first group (faster erase speed) and second group (slower erase speed), with different bias voltage levels applied to each group during the erase operation to optimize reliability for each string's characteristics
2Manufacturing precision
If multiple erase voltage pulses are supplied to all memory strings, then erase completeness improves, but memory cell reliability degrades due to excessive erase operations on already-erased cells
Solution Approach 1:
The patent implements selective bias voltage application where memory strings in the first group (faster erase) receive a first bias voltage that inhibits the second erase voltage pulse, while memory strings in the second group (slower erase) receive a second bias voltage that allows the second erase voltage pulse to proceed. This ensures complete erasure where needed while protecting already-erased cells from degradation
Solution Approach 2:
The patent uses erase verify operation results to determine which memory strings have been sufficiently erased and which require additional erasing. Based on this feedback, different bias voltages are applied to different groups of memory strings for the second erase voltage pulse, optimizing both completeness and reliability
Data Source
AI summary
A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.