Adaptive SLC Voltage Control for Hybrid Memory Block Endurance
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Solution Overview
Problem
NAND memory devices face challenges in efficiently programming and maintaining a low hybrid SLC (hSLC) ratio, which affects endurance and performance as they scale down, due to increased stress on memory cells when programming multiple bits per cell, leading to reduced endurance and varying threshold voltage margins across word lines.
Innovation Solution
The method involves determining the zone of a selected word line within a hybrid memory block to set an adaptive SLC programming voltage, applying programming pulses with verify operations as needed, and transitioning data between SLC and multiple bits per cell formats to reduce endurance damage and achieve a uniform hSLC ratio, using control circuitry to manage programming and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are programmed with multiple bits per cell to increase storage density, then storage capacity is improved, but endurance is reduced due to increased stress on memory cells
Solution Approach 1:
The memory block is divided into multiple word lines that are programmed sequentially in SLC mode. By segmenting the programming process across multiple word lines, each individual programming operation experiences reduced stress compared to programming all cells simultaneously in multi-bit mode, thereby improving overall endurance while maintaining high storage capacity utilization.
Solution Approach 2:
The programming voltage and programming mode are dynamically changed based on the word line being programmed. Different word lines may require different programming parameters to achieve optimal endurance. By adjusting programming parameters such as voltage levels and pulse durations, the system reduces stress on individual memory cells while maintaining efficient multi-bit storage capacity.
2Reliability
If hybrid SLC ratio is reduced to improve endurance, then memory cell stress is decreased, but programming complexity increases due to varying threshold voltage margins across word lines
Solution Approach 1:
Different word lines are assigned different programming characteristics based on their specific threshold voltage margins and stress conditions. Each word line receives customized programming parameters and stress levels tailored to its local characteristics, optimizing endurance for each region while simplifying the overall programming process through systematic local optimization rather than global complexity.
Solution Approach 2:
The hybrid SLC ratio and programming mode are dynamically adjusted during operation based on real-time conditions of different word lines. The system can transition between SLC and multi-bit modes for different word lines as needed, allowing flexible adaptation to varying threshold voltage margins and stress levels, thereby managing programming complexity through dynamic control rather than static configuration.
3Reliability
If uniform hSLC ratio is maintained across all word lines, then endurance is improved, but programming time increases due to sequential programming requirements
Solution Approach 1:
The memory block is programmed in periodic cycles, with each cycle programming a subset of word lines in SLC mode. By dividing the programming process into periodic cycles across different word line groups, the system maintains uniform hSLC ratio for endurance while reducing total programming time through parallel processing of multiple word lines in each cycle, rather than strictly sequential programming.
Solution Approach 2:
Word lines are pre-grouped into zones with similar characteristics before programming begins. This preliminary organization allows the system to efficiently schedule and execute programming operations across zones, maintaining uniform hSLC ratio while minimizing programming time through optimized batch processing and parallel operations within each zone.
Data Source
AI summary
The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.