Adaptive Slicer Thresholds for Recovered Clock Jitter Reduction
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Solution Overview
Problem
In high-speed digital communication systems, decision-feedback equalization (DFE) receivers face challenges in accurately recovering data due to inter-symbol interference (ISI) and jitter caused by uncertainty in the sampling clock phase, which affects the reliability of data recovery.
Innovation Solution
A circuit and method that generate adaptive threshold voltages based on the magnitude of leading bits and interference voltages caused by preceding bits, allowing for precise slicing of signals and minimizing ISI, using a combination of slicer systems and threshold circuits to adjust the sampling clock phase and reduce jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decision-feedback equalization is used to remove ISI, then data recovery accuracy is improved, but sampling clock phase uncertainty and jitter increase
Solution Approach 1:
The patent implements feedback mechanisms where the received signal is continuously monitored and fed back to adjust the sampling clock phase. The decision feedback equalizer uses previously recovered data to generate correction signals that are fed back to compensate for ISI, while the sampling clock phase is continuously adjusted based on feedback from the received signal quality to minimize jitter and uncertainty.
Solution Approach 2:
The patent dynamically adjusts sampling clock phase parameters based on signal conditions. The phase adjustment is made adaptive by changing the sampling phase angle and timing parameters in real-time according to the received signal characteristics, allowing the system to optimize data recovery accuracy while minimizing clock phase uncertainty and jitter under varying channel conditions.
2Measurement precision
If adaptive threshold adjustment is implemented, then data recovery accuracy is improved, but device complexity increases
Solution Approach 1:
The patent employs dynamic threshold adjustment where the slicing thresholds are not fixed but adapt to signal conditions in real-time. The threshold values are continuously adjusted based on the received signal amplitude and quality, allowing the system to maintain optimal data recovery accuracy across varying channel conditions while using manageable circuit complexity through adaptive control mechanisms.
3Reliability
If sampling clock phase is adjusted to minimize jitter, then signal quality is improved, but processing time increases
Solution Approach 1:
The patent implements continuous phase adjustment of the sampling clock where the phase is constantly optimized based on incoming signal conditions. This continuous adaptation ensures that the sampling clock remains synchronized with the received signal, maintaining high signal quality and minimizing jitter without requiring periodic re-synchronization that would introduce additional processing delays.
Data Source
AI summary
A circuit according to an embodiment includes a first slicer connected to an input port and a threshold circuit connected to a threshold port of the first slicer and configured to generate a first threshold voltage according to at least a first magnitude of a nominal value of a leading bit in a signal received at the input port. The first slicer is configured to slice the signal according to the first threshold voltage. In some embodiments, the threshold circuit calculates the first threshold voltage according to at least the first magnitude of the nominal value of the leading bit in the signal and a second magnitude of an interference voltage caused, in the leading bit, by a preceding bit.