Adaptive Soft-Bit Compression for NAND Reliability Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory devices face increased reliability challenges due to shrinking cell size and increased cell density, which are met by enhancing error correction capabilities through soft-bits at the expense of performance, processing time, power consumption, and complexity, with previous soft-bit compression schemes being non-adaptive and inefficient.
Innovation Solution
Adaptive soft-bit compression is implemented, where the soft-bit page size is dynamically reduced based on storage element conditions, using compressed soft-bit circuitry to determine a soft-bit delta and compression scheme, thereby reducing latency and power consumption during data transfer from the memory array to the controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft-bits are generated and transferred to improve error correction capability, then reliability is improved, but power consumption and latency increase
Solution Approach 1:
The patent extracts only the essential reliability information from soft-bits by identifying and transferring only unreliable bits (those near transition thresholds) to the controller, rather than transferring all soft-bit data. This selective extraction maintains error correction capability while reducing power consumption and latency associated with transferring large volumes of data.
2Reliability
If soft-bits are generated and transferred to improve error correction capability, then reliability is improved, but processing time increases
Solution Approach 1:
The patent extracts only the essential reliability information from soft-bits by identifying and transferring only unreliable bits (those near transition thresholds) to the controller, rather than transferring all soft-bit data. This selective extraction maintains error correction capability while reducing power consumption and latency associated with transferring large volumes of data.
3Device complexity
If fixed compression schemes are used for soft-bits, then device complexity is reduced, but adaptability to varying bit-error rates deteriorates
Solution Approach 1:
The patent implements dynamic compression schemes that adapt to varying bit-error rates and storage element conditions. The system adjusts compression parameters based on detected conditions such as temperature, read disturbances, and program/erase cycles, allowing optimal balance between compression efficiency and error correction capability under different operating conditions.
Solution Approach 2:
The patent changes compression parameters (such as compression ratio and threshold values) based on detected storage element conditions including temperature, read disturbances, and program/erase cycles. This parameter adaptation allows the system to maintain optimal performance across varying operating conditions while managing device complexity.
4Device complexity
If non-adaptive compression is used for soft-bits, then device complexity is reduced, but compression efficiency deteriorates
Solution Approach 1:
The patent implements dynamic compression schemes that adapt to varying bit-error rates and storage element conditions. The system adjusts compression parameters based on detected conditions such as temperature, read disturbances, and program/erase cycles, allowing optimal balance between compression efficiency and error correction capability under different operating conditions.
Data Source
AI summary
A memory includes, in one embodiment, NAND elements; read/write circuitry; and compressed soft-bit circuitry. The compressed soft-bit circuitry is configured to determine or receive one or more NAND conditions and then determine a soft-bit delta and select a compression scheme based on the NAND conditions. The read/write circuitry is configured to read a set of hard bits from the NAND elements and sense a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the NAND elements. The first set of soft-bits has a first fixed size, and each soft-bit of the first set of soft-bits indicates a reliability of a corresponding hard bit of the set of hard bits. The compressed soft-bit circuitry is also configured to generate a second set of soft-bits based on the selected compression scheme and output the second set of soft-bits to a controller.