Adaptive SR FET Gate Regulation for Faster Turn-Off in Deep CCM
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Solution Overview
Problem
Traditional SR controllers face challenges in achieving high efficiency and low switching stress simultaneously, especially during deep CCM or when high Rdson FETs are used, leading to long turn off delay times and increased conduction losses.
Innovation Solution
An electronic rectifier circuit with adaptive Vg regulation is introduced, which clamps the Vds of the SR FET to different regulation voltages (Vreg1 and Vreg2) based on the on-time duration of the SR FET, allowing for quick turn off and reduced stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional SR controllers use fixed Vg regulation mode, then the circuit complexity is low, but the turn off delay time increases and efficiency decreases under deep CCM conditions
Solution Approach 1:
The patent implements dynamic Vg regulation by switching between two different regulation voltages (Vreg1 and Vreg2) based on the detected on-time duration of the SR FET. The controller dynamically adjusts the gate voltage clamping level according to real-time operating conditions, transitioning from a static fixed Vg mode to a dynamic adaptive mode that optimizes turn-off performance across varying load conditions.
Solution Approach 2:
The patent changes the regulation voltage parameter from a single fixed value to multiple variable values (Vreg1 for normal conditions, Vreg2 for deep CCM conditions). By detecting the on-time duration and switching between different voltage parameters, the system adapts to different operating modes, reducing turn-off delay under heavy load while maintaining efficiency during normal operation.
2Reliability
If traditional SR controllers use fixed Vg regulation, then the device stress is high during deep CCM, but adding adaptive regulation increases circuit complexity
Solution Approach 1:
The patent segments the operating conditions into distinct modes based on on-time duration thresholds, applying different regulation strategies for different segments. By dividing the operational range into normal mode (using Vreg1) and deep CCM mode (using Vreg2), the system provides targeted protection against device stress only when needed, rather than continuously complicating the circuit.
Solution Approach 2:
The patent implements feedback control by detecting the on-time duration of the SR FET and using this information to selectively activate appropriate regulation voltages. The feedback mechanism monitors operating conditions and triggers adaptive Vg regulation only when deep CCM conditions are detected, balancing device protection with circuit simplicity.
3Loss of energy
If SR FET turn off delay is long under deep CCM, then conduction loss increases, but reducing turn off delay requires faster Vg regulation which complicates the control circuit
Solution Approach 1:
The patent applies preliminary action by pre-defining two regulation voltage levels (Vreg1 and Vreg2) that are ready to be switched based on detected conditions. Rather than continuously adjusting Vg in real-time, the system prepares appropriate voltage levels in advance and selects the suitable one based on on-time duration, simplifying the control circuit while still achieving fast turn-off when needed.
Data Source
AI summary
An electronic rectifier circuit for adaptive gate voltage regulation of a synchronous rectifier field-effect transistor is provided, the electronic rectifier circuit is configured to clamp a drain-source voltage of the SR FET to a first regulation voltage while the SR FET is switched on for less than a threshold time in a current switching cycle, and the electronic rectifier circuit is configured to clamp the Vds of the SR FET to a second regulation voltage while the SR FET is switched on for more than the threshold time in the current switching cycle, the threshold time is configured as a portion of time that the SR FET was switched on in one or more previous switching cycles, and Vreg2 is smaller than Vreg1.