Adaptive SR Turn-On Control in LLC Resonant Converters
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Solution Overview
Problem
Resonant power converters face challenges in preventing inversion currents when operating in light-load conditions, where the secondary voltage on a transformer is below the output voltage, leading to inefficiencies and potential damage.
Innovation Solution
An adaptive delay time mechanism is implemented in the rectification controller for synchronous rectification (SR) FETs, which delays the turn-on of the SR FETs until the drain-source voltage is below a threshold, preventing inversion currents by ensuring the SR FETs switch on only when conditions are optimal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SR FETs are turned on immediately when drain-source voltage drops below threshold, then rectification efficiency is improved, but inversion currents occur causing potential damage and reduced reliability
Solution Approach 1:
The patent applies preliminary action by implementing an adaptive delay mechanism that waits for the optimal moment before turning on the SR FETs. The controller monitors the drain-source voltage and delays the turn-on signal until the voltage has been below the threshold for a predetermined time period, ensuring that the FETs switch on only when inversion current risk has passed, thus preventing damage while maintaining efficiency
Solution Approach 2:
The patent uses feedback by continuously monitoring the drain-source voltage of the SR FETs and using this information to control the turn-on timing. The rectification controller adjusts the gate signal based on the real-time voltage state, creating a closed-loop control system that adapts to varying load conditions and prevents inversion currents while maximizing rectification efficiency
2Power
If the SR FETs are turned on early to capture more energy, then power transfer is improved, but inversion currents flow causing energy loss and potential damage
Solution Approach 1:
The patent applies preliminary action by implementing an adaptive delay mechanism that waits for the optimal moment before turning on the SR FETs. The controller monitors the drain-source voltage and delays the turn-on signal until the voltage has been below the threshold for a predetermined time period, ensuring that the FETs switch on only when inversion current risk has passed, thus preventing damage while maintaining efficiency
Solution Approach 2:
The patent uses feedback by continuously monitoring the drain-source voltage of the SR FETs and using this information to control the turn-on timing. The rectification controller adjusts the gate signal based on the real-time voltage state, creating a closed-loop control system that adapts to varying load conditions and prevents inversion currents while maximizing rectification efficiency
3Device complexity
If fixed turn-on timing is used for SR FETs, then control simplicity is maintained, but light-load conditions cause inversion currents reducing efficiency
Solution Approach 1:
The patent applies dynamics by transitioning from fixed turn-on timing to adaptive, condition-based control. The rectification controller dynamically adjusts the SR FET turn-on timing based on real-time monitoring of drain-source voltage and load conditions, enabling the system to optimize performance across varying operating conditions while preventing inversion currents in light-load scenarios
Solution Approach 2:
The patent uses parameter changes by adjusting the turn-on timing parameter based on operating conditions. The controller modifies the gate signal timing according to the drain-source voltage state and load level, allowing the system to adapt to different operating modes and maintain high efficiency across the full load range while preventing inversion current damage
Data Source
AI summary
Resonant power converters. Example embodiments are methods of operating a rectification controller including sensing a drain-source voltage of a synchronous rectification (SR) field effect transistor (FET); setting an adaptive delay time corresponding to a time interval between a first state transition and a second state transition, with each of the first and second state transitions corresponding to the drain-source voltage transitioning between being greater than the adaptive delay voltage and being less than the adaptive delay voltage; and driving the SR FET to a conductive state after the drain-source voltage having been less than the on-threshold voltage for longer than the adaptive delay time.