Adaptive SRAM Write Assist Circuit Using Binary Weighted Boost Capacitors
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Solution Overview
Problem
Conventional SRAM write assist circuits face challenges in maintaining reliable read and write operations as integrated circuits scale down, leading to reduced read and write margins due to voltage reductions, and are sensitive to process and temperature variations, resulting in errors and increased power consumption.
Innovation Solution
A SRAM write assist circuit utilizing binary weighted boost capacitors and transistors, controlled by encoded values based on the power supply level, which provides adaptive voltage support independent of process and temperature variations, using a bandgap voltage reference circuit to decode DC flag signals and adjust boost levels accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If access transistors are optimized for write operation by reducing on-resistance, then write performance is improved, but read performance deteriorates due to cell disturbance
Solution Approach 1:
The patent divides the write assist function into multiple segmented boost capacitors (e.g., 8 capacitors with weights 1, 2, 4, 8, 16, 32, 64, 128) that can be independently controlled. This segmentation allows precise control of the boost amount applied to bitlines during write operations, enabling the system to provide just enough assistance to overcome cell disturbance while maintaining read stability.
Solution Approach 2:
The patent implements dynamic control of boost capacitor activation based on detected voltage levels. The system dynamically adjusts which capacitors are activated during write operations, enabling the access transistors to have low on-resistance for write operations while maintaining high stability during read operations through adaptive voltage compensation.
2Length of moving object
If operation voltage is reduced to down-scale integrated circuits, then device size is reduced, but read and write margins deteriorate
Solution Approach 1:
The patent changes the voltage parameter dynamically by detecting the actual voltage level and activating appropriate boost capacitors to compensate. This allows the system to maintain adequate voltage margins for reliable read and write operations even when the base operation voltage is reduced for device scaling.
Solution Approach 2:
The patent employs a feedback mechanism where voltage detection circuits monitor the actual voltage level, and this information is used to control the activation of boost capacitors. This closed-loop feedback ensures that read and write margins are maintained despite voltage reductions from device scaling.
3Adaptability or versatility
If process and temperature variations are present, then manufacturing adaptability is improved, but operational reliability deteriorates
Solution Approach 1:
The patent implements a self-service mechanism where the system automatically detects voltage variations caused by process and temperature variations, and autonomously activates the appropriate boost capacitors to maintain reliable operation. This self-adjusting capability improves reliability without requiring external intervention or complex control circuits.
Data Source
AI summary
Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.