Adaptive Step Voltage Verification for Memory Program Loops

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Solution Overview

Problem

Current memory devices face inefficiencies in program operations due to the lack of effective methods to accurately determine the completion of programming loops, leading to potential overwriting or underwriting of data, which can result in reduced storage capacity and performance.

Innovation Solution

A memory device and method that include a program operation performer, a step voltage calculator, a reference bit determiner, and a verification result generator to calculate step voltages and determine reference fail bits based on the magnitude of step voltages, allowing for precise verification of program completion in each loop.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of program and verify operations is increased to ensure accurate program completion, then data integrity is improved, but operation time and energy consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the parameter of reference fail bit values dynamically based on the step voltage magnitude. When step voltage is large, a larger reference fail bit value is used to account for greater threshold voltage distribution shifts, reducing false verify failures. When step voltage is small, a smaller reference fail bit value provides stricter verification. This adaptive parameter adjustment ensures data integrity while minimizing unnecessary verify operations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic adjustment of verification parameters based on real-time step voltage measurements. The reference fail bit value is not fixed but changes according to the magnitude of step voltage, making the verification process adaptive to actual programming conditions. This dynamic approach optimizes the balance between verification accuracy and operation efficiency.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the reference number of fail bits is increased to reduce false verify failures, then verification accuracy is improved, but the risk of underwriting increases

Engineering Contradiction:
Improveverification accuracyVSAvoidprogram completion accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent adjusts the reference fail bit parameter based on step voltage magnitude. For large step voltages, a larger reference fail bit value compensates for threshold voltage shifts and reduces false verify failures. For small step voltages, a smaller reference fail bit value maintains strict verification to prevent underwriting. This conditional parameter adjustment resolves the contradiction between verification accuracy and program completion precision.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If fixed reference fail bit values are used in verify operations, then device complexity is reduced, but verification accuracy under varying step voltages deteriorates

Engineering Contradiction:
Improveverification logic complexityVSAvoidprogram completion detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic adjustment of reference fail bit values based on measured step voltage magnitude. The verification logic determines the step voltage size and selects appropriate reference fail bit values accordingly. This dynamic approach maintains verification accuracy across varying programming conditions without requiring overly complex fixed logic, as the adjustment is based on simple voltage magnitude comparison.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12165718B2Memory device and method of operating the same
Publication Date: 2024.12.10 SK HYNIX INC
  • US12165718B2 patent drawing
  • US12165718B2 patent drawing
  • US12165718B2 patent drawing

AI summary

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a program operation performer configured to perform a plurality of program loops on the plurality of memory cells, a step voltage calculator configured to calculate a step voltage, the step voltage being a difference of magnitude between program voltages that are applied in any two consecutive program loops, a reference bit determiner configured to determine a reference number of fail bits based on a magnitude of the step voltage, and a verification result generator configured to generate verification result information based on a result of a comparison between the reference number of fail bits and a number of on-cells, among the plurality of memory cells, identified in a verify operation that is included in a program loop, among the plurality of program loops.