Adaptive Memory Superblock Mapping Around Defective Blocks
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Solution Overview
Problem
Memory devices experience performance loss due to the presence of bad blocks in superblocks, which disrupt the assumption of equal valid block quantities, leading to overhead in managing superblocks with varying quantities of valid blocks.
Innovation Solution
Implementing a memory device with a controller that generates and maintains complete superblocks and shadow superblocks, allowing data to be written to both in different modes, thereby utilizing complete superblocks and avoiding bad blocks, thus improving overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If superblocks are used to improve write performance, then multi-plane write operations benefit from concurrent writes, but performance loss occurs when bad blocks are present in superblocks
Solution Approach 1:
The patent segments superblocks into complete superblocks (containing only good blocks) and shadow superblocks (associated with incomplete superblocks containing bad blocks). This segmentation allows the system to distinguish between superblocks that can be fully utilized and those that require partial or alternative handling, thereby maintaining performance consistency despite the presence of bad blocks.
Solution Approach 2:
The patent introduces shadow superblocks as copies or associations with incomplete superblocks. Shadow superblocks are used to track and manage the state of superblocks containing bad blocks, allowing the system to maintain performance by writing to complete superblocks while using shadow superblocks for bookkeeping and coordination.
2Adaptability or versatility
If incomplete superblocks are managed alongside complete superblocks, then bad blocks can be accommodated, but management overhead increases due to varying quantities of valid blocks
Solution Approach 1:
The patent extracts the management of incomplete superblocks from the main superblock management flow by introducing shadow superblocks. Shadow superblocks are specifically used to track and manage incomplete superblocks containing bad blocks, separating this management task from the handling of complete superblocks and reducing overall management complexity.
Solution Approach 2:
The patent implements a dynamic superblock management system where the controller adapts its behavior based on whether it is writing to complete or incomplete superblocks. The system dynamically switches between using complete superblocks for full writes and incomplete superblocks (with shadow superblock coordination) for partial writes, optimizing performance based on the actual state of superblocks.
3Adaptability or versatility
If data is written to both complete and incomplete superblocks, then data writing flexibility is improved, but latency increases due to varying write completion times
Solution Approach 1:
The patent performs preliminary actions by pre-identifying and pre-classifying superblocks into complete and incomplete categories before data writing occurs. Shadow superblocks are pre-configured to track incomplete superblocks, allowing the controller to plan write operations in advance and optimize the sequence of writes to minimize latency while maintaining flexibility.
Solution Approach 2:
The patent implements periodic coordination between complete and incomplete superblock writes through shadow superblocks. The system uses shadow superblocks to periodically check and coordinate write operations, ensuring that writes to incomplete superblocks are properly synchronized with writes to complete superblocks, thereby managing latency while maintaining writing flexibility.
Data Source
AI summary
Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.