Adaptive Synchronizer Clock Gating for Metastability Control
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Solution Overview
Problem
Existing solutions for passing signals between different timing domains, which rely on synchronous circuits with 'brute force' synchronizers, suffer from metastable states that lead to unstable outputs, high current consumption, and performance impact due to unnecessary delays, even when metastability is not present.
Innovation Solution
A method that uses a data storage circuit to synchronize asynchronous signals, allowing sufficient time for metastable recovery and disabling the clock signal to prevent metastable states from propagating, thereby reducing power consumption and improving system performance by eliminating unnecessary flip-flop chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a chain of flip-flops is used as a synchronizer circuit, then metastable states are handled, but power consumption increases and system performance degrades due to continuous delays
Solution Approach 1:
The synchronizer circuit dynamically adjusts its operation mode between synchronous and asynchronous based on metastable state detection. The circuit transitions from always-on synchronous operation to selective asynchronous operation, enabling power savings when metastability is not present while maintaining reliability when it occurs.
Solution Approach 2:
The circuit changes the clock signal parameter (enabled/disabled state) based on detected conditions. When a metastable state is detected, the clock signal to the output flip-flop is disabled, changing the operational parameters of the circuit to reduce power consumption while maintaining synchronization functionality.
2Reliability
If a chain of flip-flops is used as a synchronizer circuit, then metastable states are handled, but system performance decreases due to continuous delays
Solution Approach 1:
The synchronizer circuit dynamically adjusts its operation mode between synchronous and asynchronous based on metastable state detection. The circuit transitions from always-on synchronous operation to selective asynchronous operation, enabling performance optimization when metastability is not present while maintaining reliability when it occurs.
Solution Approach 2:
The circuit changes the clock signal parameter (enabled/disabled state) based on detected conditions. When a metastable state is detected, the clock signal to the output flip-flop is disabled, changing the operational parameters of the circuit to reduce delay and improve performance while maintaining synchronization functionality.
3Reliability
If the clock signal remains enabled continuously, then data synchronization is maintained, but power consumption increases during metastable states
Solution Approach 1:
The circuit uses feedback from the metastable state detection logic to control the clock enable signal. The detection circuit monitors the output of the first flip-flop and provides feedback to the clock enable logic, which adjusts the clock signal to the second flip-flop based on the detected state, thereby reducing power consumption during metastable conditions.
Solution Approach 2:
The synchronizer circuit automatically detects and responds to metastable states without external intervention. The internal detection circuit identifies metastable conditions and self-adjusts the clock signal accordingly, enabling the circuit to serve itself in optimizing power consumption while maintaining synchronization.
4Measurement precision
If voltage threshold detection is used to detect metastable states, then accurate detection is achieved, but circuit complexity increases
Solution Approach 1:
The detection circuit is segmented into multiple independent voltage threshold comparison stages. Each threshold circuit independently compares the output voltage against a reference threshold, and their combined output determines the metastable state. This segmentation allows accurate detection while keeping each individual comparison circuit simple and modular.
Data Source
AI summary
A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.