Adaptive Syndrome Decoding for Direct-Input Memory Redundancy
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Solution Overview
Problem
The existing memory devices face increased latency in error correction operations due to the lengthy data path required for transferring redundant data bits to error correction circuitry, which can delay retrieval operations.
Innovation Solution
Implementing a direct-input redundancy scheme where redundant data bits are directly input into an error correction circuit dedicated to the redundant data plane, coupled with adaptive syndrome decoders that selectively process inputs based on the type of data being decoded, reducing the data path length and propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant data bits are transferred through the standard data path to error correction circuitry, then error correction can be performed, but the latency of retrieval operations increases due to the lengthy data path
Solution Approach 1:
The patent segments the error correction system into two independent pathways: one for regular data bits and one for redundant data bits. The redundant data plane has its own dedicated error correction circuitry that operates independently, allowing simultaneous error correction for both regular and redundant data without interfering with each other, thus reducing overall latency while maintaining reliability
Solution Approach 2:
The patent introduces a data plane selector as an intermediary component that routes either regular data or redundant data to the appropriate error correction circuitry. This selector enables the system to efficiently manage the data flow and choose the optimal path based on whether error correction is needed, thereby reducing unnecessary delays in retrieval operations
2Speed
If a dedicated error correction circuit is created for redundant data, then propagation delay is reduced, but device complexity increases
Solution Approach 1:
The patent designs the redundant data plane and its error correction circuitry to be universal and interchangeable with the regular data plane. The same types of circuits and components are used for both data planes, allowing the system to maintain reduced propagation delay through dedicated pathways while avoiding excessive complexity by reusing proven, standardized error correction building blocks
Solution Approach 2:
The patent applies local quality by providing dedicated error correction resources specifically where needed (in the redundant data plane) rather than uniformly across the entire system. This targeted approach reduces propagation delay for redundant data correction while minimizing overall device complexity by avoiding redundant error correction capabilities in every data path
Data Source
AI summary
Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.