Adaptive TDC Gating for Low-Spur PLL Phase Quantization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-to-digital converters (TDCs) in digital phase-locked loops face challenges with high current consumption due to long physical lengths, leading to receiver desensitization and degraded phase quantization accuracy, especially when dealing with high spectral purity requirements in modern communication systems.
Innovation Solution
An adaptive TDC system that incorporates adaptive gating circuitry to minimize the transparency window and adaptive supply circuitry to vary the supply voltage, allowing fewer delay elements to cover a larger range of operational frequencies while compensating for process corner variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC uses a long physical length with many delay elements to cover the full cycle of the LO signal, then the phase quantization range is sufficient, but the current consumption increases and receiver desensitization occurs
Solution Approach 1:
The patent implements adaptive gating that dynamically adjusts the transparency window based on the detected phase difference. The gating signal is adapted to close the transparency window when the phase difference is small, thereby reducing current consumption while maintaining sufficient phase quantization range when needed.
Solution Approach 2:
The patent changes the gating parameter (transparency window duration) adaptively based on operating conditions. By modifying the gating signal's transparency window according to the phase difference detection, the system optimizes current consumption while preserving measurement capability when required.
2Measurement precision
If the TDC uses a long physical length to achieve high resolution phase quantization, then the phase quantization accuracy is improved, but fractional spurs increase causing receiver desensitization
Solution Approach 1:
The adaptive gating dynamically adjusts the transparency window based on the phase difference, reducing the duration during which fractional spurs can be generated. This dynamic adjustment maintains measurement accuracy when needed while minimizing spur generation during normal operation.
Solution Approach 2:
The gating signal operates periodically with adaptive transparency windows that are timed to coincide with relevant phase detection events. This periodic gating structure reduces continuous current flow and associated fractional spurs while maintaining detection capability.
3Ease of operation
If the TDC uses a fixed transparency window, then the circuit operation is simple, but it cannot adapt to different LO frequencies and process corners
Solution Approach 1:
The patent implements feedback mechanisms where the detected phase difference and frequency information are used to adjust the gating signal's transparency window. This feedback loop enables the circuit to adapt to different LO frequencies and process corners while maintaining relatively simple operation through automated adjustment.
Solution Approach 2:
The TDC circuit automatically adjusts its own gating parameters based on detected signal characteristics. The system serves itself by using its own output (phase difference detection) to control its input gating, eliminating the need for external complex control while achieving adaptability.
Data Source
AI summary
Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.