Adaptive TDC Gating and Supply Control for Low-Spur PLL Phase Sensing
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Solution Overview
Problem
Time-to-digital converters (TDCs) in digital phase-locked loops face high current consumption due to the need for long delay chains to achieve high resolution phase-quantization, leading to aggressive current spikes and fractional spurs that degrade phase quantization accuracy and desensitize receivers.
Innovation Solution
An adaptive TDC system with adaptive gating circuitry to minimize the transparency window and adaptive supply circuitry to vary the supply voltage, allowing fewer delay elements to cover a larger range of operational frequencies while compensating for process corner variations, thereby reducing current consumption and maintaining phase quantization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay chain length is increased to achieve high resolution phase-quantization, then the phase quantization accuracy is improved, but the current consumption increases aggressively
Solution Approach 1:
The patent applies dynamics by making the delay chain length adjustable rather than fixed. The TDC circuit dynamically adapts its delay chain length based on the input signal frequency and desired resolution requirements. At higher frequencies, fewer delay elements are needed, reducing current consumption, while at lower frequencies, the full chain provides maximum resolution, resolving the contradiction between constant high resolution and variable current consumption.
Solution Approach 2:
The patent changes the parameter of delay chain length based on operating conditions. By varying the number of active delay elements according to the input signal characteristics and required phase resolution, the system achieves high measurement precision only when necessary, thereby reducing overall current consumption while maintaining phase quantization accuracy when needed.
2Measurement precision
If the delay chain length is increased to cover the full cycle of high frequency LO signal, then the phase quantization range is improved, but fractional spurs are generated that degrade accuracy
Solution Approach 1:
The patent uses dynamics to adapt the delay chain length to the specific LO signal frequency being measured. Rather than using a fixed long chain that causes fractional spurs at certain frequencies, the system dynamically adjusts the chain length to match the signal characteristics, eliminating fractional spurs while maintaining sufficient phase quantization range and accuracy for each specific frequency.
Solution Approach 2:
The patent converts the potential harm of fractional spurs into a benefit by using the known relationship between LO frequency and required delay chain length. By intentionally limiting the chain length based on frequency detection, the system prevents fractional spur generation while still achieving accurate phase measurement, turning what would be a harmful effect into a controlled design parameter.
3Measurement precision
If the delay chain length is increased to maintain resolution at low frequencies, then the phase quantization precision is improved, but the device length increases
Solution Approach 1:
The patent applies dynamics by making the delay chain length variable rather than fixed. The TDC circuit dynamically adapts its delay chain length based on the input signal frequency and desired resolution requirements. At higher frequencies, fewer delay elements are needed, reducing current consumption, while at lower frequencies, the full chain provides maximum resolution, resolving the contradiction between constant high resolution and variable current consumption.
Solution Approach 2:
The patent changes the parameter of delay chain length based on operating conditions. By varying the number of active delay elements according to the input signal characteristics and required phase resolution, the system achieves high measurement precision only when necessary, thereby reducing overall current consumption while maintaining phase quantization accuracy when needed.
Data Source
AI summary
Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.