Adaptive TDC Circuit for PLL Phase Correction Across Wide Time Ranges
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in achieving high resolution without increasing circuitry, which leads to accuracy reduction and noise interference.
Innovation Solution
The implementation of a self-adaptive time-to-digital converter (TDC) circuit that switches between coarse and fine modes based on the offset time, using a fractional bit for quantization error compensation to maintain accuracy with reduced circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher resolution digital adjustment signal is used, then PLL accuracy is improved, but circuit area and power consumption increase
Solution Approach 1:
The TDC circuit is divided into multiple sub-TDC circuits, each handling a specific time range with appropriate resolution. The circuit segments the measurement task across multiple specialized units rather than using a single high-resolution circuit for all ranges, thereby achieving high accuracy without proportionally increasing overall circuit area.
Solution Approach 2:
The TDC circuit dynamically switches between different sub-TDC circuits based on the detected time period magnitude. When the time period is large, a coarser sub-TDC is used; when it's small, a finer sub-TDC is activated. This dynamic adaptation allows the circuit to maintain high resolution only when needed, reducing average circuit area and power consumption.
2Measurement precision
If higher resolution digital adjustment signal is used, then PLL accuracy is improved, but power consumption increases
Solution Approach 1:
The circuit dynamically activates only the necessary sub-TDC circuits based on the current measurement requirements. By switching between different resolution levels adaptively, the circuit consumes power only for the resolution level currently needed, avoiding continuous high power consumption associated with always-running high-resolution circuits.
Solution Approach 2:
The circuit changes its operational parameters (resolution level) based on the input signal characteristics. By adjusting the effective resolution of the TDC circuit to match the actual time period being measured, the system optimizes power consumption while maintaining sufficient accuracy for each specific measurement scenario.
3Device complexity
If lower resolution digital adjustment signal is used, then circuit area is reduced, but PLL accuracy and noise interference performance deteriorate
Solution Approach 1:
The measurement range is segmented into multiple intervals, with each sub-TDC circuit optimized for a specific segment. This allows the system to use lower resolution (smaller circuit area) for less critical measurements while maintaining high resolution for critical measurements, thereby improving overall accuracy without proportionally increasing total circuit area.
Solution Approach 2:
Different parts of the TDC circuit (sub-TDC circuits) have different resolution qualities tailored to their specific measurement ranges. The circuit applies high resolution locally where it matters most (small time periods requiring precision) and uses lower resolution locally where it's sufficient (large time periods), optimizing the balance between accuracy and circuit area.
4Measurement precision
If fixed high resolution TDC circuit is used, then PLL accuracy is improved, but adaptability to different time periods is reduced
Solution Approach 1:
The TDC circuit is designed to dynamically adapt its resolution characteristics based on the input time period. By switching between different sub-TDC circuits with different resolution levels, the system maintains high accuracy across a wide range of time periods rather than being optimized for a single fixed range, thereby improving both accuracy and adaptability simultaneously.
Solution Approach 2:
The multi-sub-TDC circuit structure provides universal functionality across different time period ranges. Each sub-TDC circuit serves a specific function for a particular range, and together they provide a universal solution that handles various time periods effectively, making the PLL adaptable to different operating conditions while maintaining accuracy.
Data Source
AI summary
A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the digitally controlled oscillator (DCO) to correct for the phase/frequency difference to synchronize the generated signal with the reference signal. In an aspect, an adaptive TDC circuit generates a first digital indication in a coarse mode when the offset time is above a threshold and generates a second digital indication in a fine mode when the offset time is below the threshold. The first digital indication and the second digital indication each comprise a same number of bits, and the first digital indication is normalized to the second digital indication for the digital output of the adaptive TDC circuit. A fractional bit may be employed to compensate for a quantization error.