Adaptive TDC Circuit for PLL Phase Resolution With Lower Area

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Solution Overview

Problem

Existing phase-locked loops (PLLs) face challenges in achieving high resolution without increasing circuitry, which leads to accuracy reduction and noise interference.

Innovation Solution

An adaptive time-to-digital converter (TDC) circuit with self-adaptive time granularity, switching between coarse and fine modes based on the offset time, uses a fractional bit for quantization error compensation to maintain accuracy with reduced circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If higher resolution digital adjustment signal is used, then PLL accuracy is improved, but circuit area and power consumption increase

Engineering Contradiction:
ImprovePLL accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The TDC circuit is divided into multiple sub-TDC circuits, each handling a specific time range. This segmentation allows the system to achieve high resolution for small time differences using only a subset of sub-TDC circuits, rather than requiring all circuits to operate simultaneously, thus reducing the active circuit area while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TDC circuit dynamically switches between different sub-TDC circuits based on the magnitude of the time difference being measured. For small time differences, a high-resolution sub-TDC circuit is activated; for large time differences, a lower-resolution sub-TDC circuit is used. This dynamic adaptation optimizes the balance between accuracy and circuit resource utilization.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If higher resolution digital adjustment signal is used, then PLL accuracy is improved, but power consumption increases

Engineering Contradiction:
ImprovePLL accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The TDC circuit is divided into multiple sub-TDC circuits, each handling a specific time range. This segmentation allows the system to achieve high resolution for small time differences using only a subset of sub-TDC circuits, rather than requiring all circuits to operate simultaneously, thus reducing the active circuit area while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TDC circuit dynamically switches between different sub-TDC circuits based on the magnitude of the time difference being measured. For small time differences, a high-resolution sub-TDC circuit is activated; for large time differences, a lower-resolution sub-TDC circuit is used. This dynamic adaptation optimizes the balance between accuracy and circuit resource utilization.

Inventive Principle:
Principle #15Dynamics

3Area of stationary object

If lower resolution digital adjustment signal is used, then circuit area is reduced, but PLL accuracy and signal quality deteriorate

Engineering Contradiction:
Improvecircuit areaVSAvoidPLL accuracy
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The TDC circuit is divided into multiple sub-TDC circuits, each handling a specific time range. This segmentation allows the system to achieve high resolution for small time differences using only a subset of sub-TDC circuits, rather than requiring all circuits to operate simultaneously, thus reducing the active circuit area while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TDC circuit dynamically switches between different sub-TDC circuits based on the magnitude of the time difference being measured. For small time differences, a high-resolution sub-TDC circuit is activated; for large time differences, a lower-resolution sub-TDC circuit is used. This dynamic adaptation optimizes the balance between accuracy and circuit resource utilization.

Inventive Principle:
Principle #15Dynamics

4Area of stationary object

If lower resolution digital adjustment signal is used, then circuit area is reduced, but noise interference increases

Engineering Contradiction:
Improvecircuit areaVSAvoidnoise interference
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The TDC circuit is divided into multiple sub-TDC circuits, each handling a specific time range. This segmentation allows the system to achieve high resolution for small time differences using only a subset of sub-TDC circuits, rather than requiring all circuits to operate simultaneously, thus reducing the active circuit area while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TDC circuit dynamically switches between different sub-TDC circuits based on the magnitude of the time difference being measured. For small time differences, a high-resolution sub-TDC circuit is activated; for large time differences, a lower-resolution sub-TDC circuit is used. This dynamic adaptation optimizes the balance between accuracy and circuit resource utilization.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12216434B2Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods
Publication Date: 2025.02.04 MICROSOFT TECHNOLOGY LICENSING LLC
  • US12216434B2 patent drawing
  • US12216434B2 patent drawing
  • US12216434B2 patent drawing

AI summary

A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the digitally controlled oscillator (DCO) to correct for the phase/frequency difference to synchronize the generated signal with the reference signal. In an aspect, an adaptive TDC circuit generates a first digital indication in a coarse mode when the offset time is above a threshold and generates a second digital indication in a fine mode when the offset time is below the threshold. The first digital indication and the second digital indication each comprise a same number of bits, and the first digital indication is normalized to the second digital indication for the digital output of the adaptive TDC circuit. A fractional bit may be employed to compensate for a quantization error.