Adaptive Temporal Filtering for Single Event Effect Mitigation
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Solution Overview
Problem
Conventional methods for mitigating single event effects (SEEs) in space-based digital integrated circuits, such as single event upsets (SEUs), data SETs, and clock SETs, are inadequate as they either fail to protect against all types of SEEs or require custom designs that are not adaptable to varying process, voltage, and temperature (PVT) conditions, leading to incomplete filtering or performance degradation.
Innovation Solution
An adaptive temporal filtering system that uses a master delay line and a slave delay line to generate three independent clock signals with precise offsets, combined with a triple voting register structure, to mitigate the effects of SEEs by ensuring that only one storage element is affected by upsets within a target pulse width, thereby maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional majority voter protection is used for SEUs, then storage element corruption is protected, but data path SETs and clock SETs remain unprotected
Solution Approach 1:
The system segments the clock distribution into three independent clock trees, each feeding a separate storage element. This segmentation ensures that a clock SET affecting one tree does not propagate to all storage elements, enabling protection against clock SETs while maintaining the majority voter structure for SEU protection.
Solution Approach 2:
The patent introduces an intermediary mechanism (independent clock trees with offset timing) between the clock signal and storage elements. This intermediary structure filters clock SETs before they reach the storage elements, while still allowing valid clock signals to properly trigger storage operations.
2Reliability
If fixed filter logic is used for data SETs, then filtering can be applied, but the filter must be set for larger than desired pulse widths to compensate for PVT variations, adversely affecting circuit performance
Solution Approach 1:
The system dynamically adapts to PVT variations by using three independent clock trees with offset timing instead of fixed filter logic. The offset timing automatically adjusts to PVT conditions, providing effective data SET filtering without requiring oversized filter settings that would degrade circuit performance.
Solution Approach 2:
The patent changes the timing parameter of clock signals by introducing offsets between the three clock trees. This parameter change enables the system to maintain effective filtering across varying PVT conditions without fixing the filter for worst-case scenarios, thereby preserving circuit performance.
3Reliability
If custom clock splitter is used for clock SETs, then clock signal filtering is achieved, but the structure is unique to particular clock architecture and not easily ported to various digital integrated circuit designs
Solution Approach 1:
The patent implements a universal clock distribution architecture using three independent clock trees that can be integrated into various digital integrated circuit designs. This universal structure provides clock SET protection while maintaining compatibility with different clock architectures, unlike custom clock splitters that are specific to particular designs.
4Device complexity
If single pair of clock phases is fed to storage elements, then clock distribution is simplified, but common output circuitry remains subject to upsets and affected by clock SETs
Solution Approach 1:
The system segments the clock distribution into three independent clock trees instead of using a single pair of clock phases. This segmentation isolates the clock paths so that a SET in one tree does not affect the others, protecting against clock SETs while maintaining manageable complexity.
Data Source
AI summary
Technologies are described herein for mitigating the effects of single event effects or upsets on digital semiconductor device data paths and clocks utilizing an adaptive temporal filter. The adaptive temporal filter includes a master delay line and a slave delay line to generate two output clock signals that remain unaffected by variations in process, voltage and temperature (PVT) conditions. The adaptive temporal filter supplies the three independent clock signals having a programmable phase relationship, to a triple voting register structure for storing and outputting an uncorrupted data value using a majority voter.