Self-Adaptive Termination Impedance Circuit for Memory Bus Matching
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in maintaining optimal termination impedances due to changes in temperature and bus voltage, leading to impedance mismatches that affect data transmission quality and require frequent calibration, which is power-consuming and time-intensive.
Innovation Solution
A self-adaptive on-die termination impedance circuit that automatically adjusts termination impedances based on feedback signals from temperature and bus voltage changes, using impedance adjustment circuits with pull-up and pull-down units controlled by calibration codes and impedance adjustment signals to maintain matched impedance with the data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent calibration is performed to maintain optimal termination impedances, then data transmission quality is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic impedance adjustment by detecting changes in operating conditions (temperature, bus voltage) and automatically adjusting termination impedance values in real-time. This allows the system to maintain optimal impedance matching without requiring frequent full calibrations, thereby reducing power consumption while preserving data transmission quality.
Solution Approach 2:
The patent employs feedback mechanisms where the system continuously monitors operating conditions and adjusts termination impedance based on detected changes. This closed-loop approach enables the system to respond to environmental variations automatically, maintaining transmission quality without exhaustive recalibration cycles that would increase power consumption.
2Measurement precision
If calibration is performed sequentially for each memory device, then termination impedance accuracy is improved, but calibration time increases
Solution Approach 1:
The patent performs preliminary impedance adjustments by detecting changes in operating conditions and pre-adjusting termination impedance values before actual data transmission begins. This preliminary action reduces the need for time-consuming sequential calibrations of each memory device while maintaining accurate impedance matching.
Solution Approach 2:
The patent combines impedance adjustment operations across multiple memory devices by implementing system-level monitoring of operating conditions and applying unified impedance corrections. This merging of calibration operations reduces the total calibration time compared to strictly sequential per-device calibration while maintaining impedance accuracy.
3Use of energy by moving object
If calibration codes are stored and reused, then power consumption is reduced, but impedance matching accuracy deteriorates due to temperature and voltage changes
Solution Approach 1:
The patent transitions from static reuse of calibration codes to dynamic adjustment of termination impedance based on real-time detection of temperature and bus voltage changes. This dynamic approach maintains impedance matching accuracy under varying operating conditions while avoiding the high power consumption associated with frequent full recalibration cycles.
Solution Approach 2:
The patent changes the termination impedance parameters in response to detected variations in operating conditions (temperature, bus voltage). By adjusting impedance values based on these parameter changes, the system maintains accurate impedance matching without requiring complete recalibration, thus reducing power consumption while preserving matching accuracy.
Data Source
AI summary
A memory system includes a memory device with a termination circuit providing a termination impedance for a data signal in the memory device. The device also includes a calibration circuit configured to set the termination impedance to a predetermined value. The device further includes an impedance adjustment circuit configured to adjust the termination impedance based on a feedback signal indicating a change in the termination impedance due to at least one of a change in a temperature of the memory device or a change in voltage of a voltage bus in the memory device.