Adaptive-Threshold ADC for GPS CW Interference Rejection
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Solution Overview
Problem
GPS receivers face significant challenges in rejecting constant envelope continuous-wave interference, which degrades signal-to-noise ratio, due to the requirement for large external capacitors in analog-to-digital converters (ADCs) that increase costs and are inefficient in managing dynamic gain ranges.
Innovation Solution
An ADC with adaptive thresholds and a digital automatic gain control (AGC) loop that uses a comparator circuit, counter, integrator, and threshold generator to adjust thresholds dynamically, allowing for effective interference rejection and optimal signal amplification without the need for large external capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ADC with analog AGC loop is used, then the circuit can maintain stable operation, but a large external capacitor is required which increases cost and device complexity
Solution Approach 1:
The patent replaces the analog AGC loop with a digital AGC loop that uses digital signal processing to regulate the gain of the variable gain amplifier. The digital controller monitors the output signal level and adjusts the VGA gain accordingly, eliminating the need for large external capacitors while maintaining stable operation.
Solution Approach 2:
The patent changes the operating parameters by implementing digital control of the AGC loop, allowing dynamic adjustment of the VGA gain through digital signal levels rather than analog voltage control. This parameter change enables the system to maintain stability without requiring large capacitance values.
2Stability of the object's composition
If the AGC loop uses a large capacitor to maintain millisecond time constant, then the gain regulation is stable, but the overall cost of the circuitry increases
Solution Approach 1:
The patent substitutes the analog capacitor-based time constant implementation with a digital implementation using a digital controller and programmable logic. The digital AGC loop achieves the required millisecond time constant through software timing and digital filtering, eliminating the need for large physical capacitors and reducing manufacturing costs.
Solution Approach 2:
The digital controller performs multiple functions including AGC gain regulation, interference detection, and adaptive filtering within a single integrated circuit. This multi-functionality consolidates what would otherwise require separate analog components, reducing overall circuit complexity and cost while maintaining stable gain regulation.
3Power
If conventional filtering is used before ADC, then the signal can be amplified, but constant envelope CW interference causes significant SNR degradation
Solution Approach 1:
The patent implements a feedback mechanism where the digital controller continuously monitors the digitized signal for signs of CW interference and dynamically adjusts the AGC loop parameters and filtering characteristics. This feedback enables the system to distinguish between desired signals and interference, maintaining proper signal amplification while mitigating the harmful effects of constant envelope interference.
Solution Approach 2:
The patent introduces dynamic adaptability by making the AGC loop and filtering characteristics可调 (adjustable) based on real-time signal conditions. The digital controller can dynamically change the loop bandwidth, gain scheduling, and filtering parameters to optimize performance for different signal types, effectively handling both weak GPS signals and constant envelope interference.
Data Source
AI summary
An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.