Adaptive Tile Sizing for IC Parasitic Extraction Accuracy
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Solution Overview
Problem
Existing parasitic extraction tools struggle to accurately calculate parasitic effects in IC designs with omni-directional and curvilinear interconnects due to high computational burden and memory consumption, especially when dealing with large designs and manufacturing non-idealities.
Innovation Solution
A layout verification tool that divides the IC design layout into tiles, computes parasitic parameters using a field solver or machine-trained network for interconnect segments within neighboring tiles, and integrates these values to obtain overall parasitic values for the full interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If field solvers are used to compute parasitic values for complete IC designs, then measurement precision is improved, but productivity deteriorates due to high computational burden and memory consumption
Solution Approach 1:
The patent divides the IC design layout into multiple tiles, where each tile contains a subset of interconnect segments. The field solver computes parasitic values for each tile independently, then these values are integrated to obtain overall parasitic values for the complete design. This segmentation enables parallel processing and reduces memory consumption while maintaining extraction accuracy.
2Measurement precision
If smaller panels are used in field solver input data, then measurement precision is improved, but productivity deteriorates due to increased run-time and memory usage
Solution Approach 1:
The patent segments the interconnect structures into smaller panels within each tile, which are then processed independently by the field solver. This allows the use of fine-grained panels for accurate capacitance calculation within each tile while keeping the overall memory footprint manageable through parallel processing of multiple tiles.
Solution Approach 2:
The patent transitions from processing the entire design as a single 3D structure to processing multiple independent 2D tile cross-sections. This dimensional decomposition allows smaller panels to be used within each tile without proportionally increasing total memory usage, as each tile is processed separately and results are integrated.
3Productivity
If approximate solutions using pattern matching techniques are used, then productivity is improved, but measurement precision deteriorates for omni-directional and curvilinear interconnects
Solution Approach 1:
The patent segments the design into tiles that can be processed using efficient pattern matching techniques, while critical regions are identified and processed with more accurate field solver methods. This hybrid approach maintains productivity for standard patterns while improving precision for complex omni-directional and curvilinear interconnects.
Data Source
AI summary
Some embodiments provide a method calculating parasitic parameters for an IC design layout having interconnects that traverse multiple interconnect layers. The interconnects represent wires that traverse multiple wiring layers of the IC. The method analyzes congestion of interconnects in a layer of the design layout to identify at least a first region of the layer having a first density of interconnects and a second region of the layer having a second, greater density of interconnects. The method divides the design layout into multiple tiles such that each interconnect of a set of the interconnects is divided into multiple interconnect segments each of which is located in a respective tile. Tiles in the first region are larger than tiles in the second region to account for the different interconnect densities. The method computes parasitic values that express parasitic effects exerted on the interconnect segments on a per-tile basis.