Adaptive Time-Multiplexing Memory Controller for Multi-Core Interference
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Solution Overview
Problem
As the number of processor cores in computer systems increases, memory access conflicts become more likely, leading to reduced spatial and temporal locality in memory reference streams, resulting in increased power consumption and decreased efficiency due to additional page operations and interference between threads.
Innovation Solution
Implementing adaptive time-multiplexing in memory systems, where the memory controller issues multiple memory references from one processor core back-to-back, utilizing locality to enhance power consumption and performance, and using hints or tokens to determine when to activate and deactivate time-multiplexing based on interference and hit rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of processor cores is increased, then computing power and processing capability are improved, but memory access conflicts increase leading to reduced spatial and temporal locality
Solution Approach 1:
The patent implements time-multiplexed memory access where processor cores are granted periodic access slots to the memory system. During each slot, a selected core can issue multiple memory references without interference from other cores, restoring spatial and temporal locality. This periodic scheduling eliminates memory access conflicts while maintaining support for multiple cores.
2Loss of energy
If time-multiplexing is activated to reduce memory conflicts, then page-hit rates increase and power consumption decreases, but memory access latency increases
Solution Approach 1:
The patent dynamically adjusts the time-multiplexing configuration based on detected memory access patterns and interference levels. When interference is high, time-multiplexing is activated to reduce conflicts and power consumption. When interference is low, the system switches to concurrent access mode to minimize latency. This dynamic adaptation allows the system to optimize between power efficiency and speed based on actual workload conditions.
3Productivity
If concurrent memory access from multiple cores is allowed, then memory bandwidth utilization is improved, but interference between threads increases causing more page operations
Solution Approach 1:
The patent introduces a memory controller that acts as an intermediary between processor cores and the memory system. The controller monitors memory access patterns, detects interference between threads, and manages access arbitration. When interference is detected, the controller implements time-multiplexing to separate access streams, eliminating harmful interference while maintaining efficient memory bandwidth utilization through coordinated access scheduling.
Data Source
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AI summary
The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.