Adaptive Timing Margin Calibration Using Gray Code Signals
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Solution Overview
Problem
Integrated circuits with complex clock domains face performance degradation when operating voltage and timing margins change, as existing clock-stop schemes are ineffective in preventing operation errors.
Innovation Solution
A memory device and application processor system that adaptively calibrate timing margins using gray code signals, allowing operation timing adjustments without stopping the clock, by determining optimal operating power levels and generating corresponding gray code signals to manage voltage and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock-stop scheme is used to adjust timing margin during voltage changes, then operation errors are prevented in simple clock domains, but performance degradation occurs in complex clock domains with many clock signals
Solution Approach 1:
The patent applies dynamics by making the clock signal adaptable - it can be stopped when needed (for reliability) but continues running when not needed (for performance). The clock stop control circuit dynamically controls clock signals based on whether timing margin adjustment is required, allowing the system to switch between operational modes as conditions change.
Solution Approach 2:
The patent segments the clock domain into multiple independent clock signals, each可控 independently. Instead of stopping all clocks or using a global clock-stop scheme, the system can selectively stop only the specific clock signals that are affected by timing margin changes, while other clock signals continue to operate, thus maintaining performance in complex clock domains.
2Use of energy by moving object
If operating voltage is changed to adjust power consumption, then power efficiency improves, but timing margin must be recalibrated which may cause operation errors
Solution Approach 1:
The patent applies preliminary action by adjusting the timing margin before changing the operating voltage. The timing margin adjustment circuit pre-calibrates the timing parameters according to the target voltage level, and only after the timing margin is properly adjusted does the voltage change occur. This prevents operation errors by ensuring the timing is already optimized for the new voltage level.
Solution Approach 2:
The patent uses feedback through a voltage detection circuit that monitors the actual operating voltage and provides this information to the timing margin adjustment circuit. Based on the detected voltage level, the system automatically adjusts the timing margin to the appropriate value, creating a closed-loop control system that ensures reliable operation across different voltage conditions.
3Productivity
If timing margin is adjusted adaptively without stopping clock, then performance is maintained in complex clock domains, but operation errors may occur during voltage transitions
Solution Approach 1:
The patent introduces a clock stop control circuit as an intermediary between the voltage change and the clock signals. This intermediary circuit coordinates the timing margin adjustment with clock signal control, ensuring that clocks are stopped only when absolutely necessary and for the minimum required time. This mediator enables the system to maintain performance while preventing operation errors during voltage transitions.
Data Source
AI summary
An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.