Adaptive TLB Page Sizing for Fewer GPU Unified Memory Misses
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Solution Overview
Problem
TLB misses and page fault exceptions cause significant performance penalties, particularly in graphics processing units (GPUs) when used as accelerators for central processing units (CPUs) implementing unified memory spaces, leading to inefficiencies in data processing.
Innovation Solution
Implementing an adaptive page size mechanism in translation lookaside buffers (TLBs) to optimize memory address translation, reducing the frequency of TLB misses and page faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a unified memory space is implemented in GPU-accelerated systems, then memory management is simplified and versatility is improved, but TLB misses and page fault exceptions increase causing significant performance penalties
Solution Approach 1:
The patent implements dynamic page size selection in the TLB, where the system can adaptively choose between different page sizes (e.g., 4KB, 64KB, 1MB) based on the specific memory access patterns and workload characteristics. This dynamic adaptation allows the unified memory space to efficiently handle both fine-grained and coarse-grained memory accesses, reducing TLB misses without sacrificing the versatility of unified memory management.
Solution Approach 2:
The invention changes the parameter of page size from a fixed value to a variable that can be adjusted based on system needs. By implementing multiple page size options and selecting the appropriate size for different memory regions and access patterns, the system resolves the contradiction between unified memory space benefits and performance penalties from TLB misses.
2Device complexity
If fixed page size is used in TLB, then device complexity is reduced and ease of manufacture is improved, but adaptability to different memory access patterns deteriorates leading to increased TLB misses
Solution Approach 1:
The TLB is designed with dynamic page size selection capability, allowing it to adapt to different memory access patterns without requiring a completely different structure for each pattern. The system can switch between fixed and variable page sizes based on workload characteristics, maintaining relative structural simplicity while improving adaptability.
3Device complexity
If larger page sizes are used in TLB, then the number of TLB entries required is reduced and device complexity is lowered, but memory access precision and ability to handle fine-grained memory operations deteriorates
Solution Approach 1:
The system implements variable page size support, allowing it to change the page size parameter based on the specific memory operation requirements. For fine-grained memory operations, smaller page sizes (e.g., 4KB) provide precise address translation, while for large memory regions, larger page sizes (e.g., 1MB) reduce the number of TLB entries needed. This parameter adaptability resolves the contradiction between TLB size and translation precision.
Data Source
AI summary
Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.