Adaptive Traversal Patterns for Multiplanar Reformatting Memory Access

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Solution Overview

Problem

Existing multiplanar reformatting techniques face inefficiencies in memory access and cache misses, leading to latency and view-dependent speed performance, particularly when dealing with large volumes and non-aligned reformatting planes.

Innovation Solution

The method involves determining the intersection boundary between the volume and reformatting planes, selecting processing patterns based on alignment, and distributing scanlines across multiple processors to optimize memory access and traversal patterns, reducing cache misses and view dependency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional volume rendering optimization techniques are used, then processing speed may be improved through preprocessing or graphics hardware utilization, but memory access efficiency and cache misses remain unaddressed

Engineering Contradiction:
Improveprocessing speedVSAvoidlatency from memory access
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent changes the traversal parameters and memory access patterns by adapting the traversal direction and pattern based on the alignment between volume slices and reformatting planes. This dynamic parameter adjustment optimizes memory access efficiency without requiring preprocessing or additional memory allocation, directly addressing the latency issue while maintaining processing speed.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention introduces dynamic adaptation of traversal patterns based on runtime conditions (alignment between volume and plane). Instead of static preprocessing approaches, the system dynamically selects optimal traversal patterns during execution, allowing it to respond to different viewing scenarios and minimize cache misses without sacrificing processing speed.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If a spread memory layout is used to address memory access efficiency, then cache misses may be reduced, but additional memory allocation up to four times the original volume is required

Engineering Contradiction:
Improvecache missesVSAvoidmemory allocation
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

Instead of physically reorganizing the volume data in memory (which would require additional memory allocation), the patent creates a virtual copy of the optimized access pattern through software-based traversal adaptation. The system copies the effect of an optimized memory layout by dynamically adjusting traversal patterns to match the existing slice-based layout, achieving cache efficiency without additional memory overhead.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent changes the traversal parameters to match the existing memory layout rather than changing the memory layout itself. By adapting the traversal direction and pattern based on alignment conditions, the system achieves efficient memory access using the original volume data structure, avoiding the need for additional memory allocation while reducing cache misses.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If the volume memory layout is changed to bricked volume layout, then memory access efficiency may be improved, but additional large volume allocation is required since input volume is read-only

Engineering Contradiction:
Improvememory access efficiencyVSAvoidadditional volume allocation
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The patent creates a virtual representation of the optimized access pattern through software traversal adaptation rather than physically copying or reorganizing the volume data. This allows the system to achieve bricked-volume-like memory access efficiency while working with the read-only slice-based input format, avoiding additional memory allocation entirely.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The invention introduces an intermediary layer (the adaptive traversal control logic) between the processor and the volume data. This intermediary dynamically selects and executes appropriate traversal patterns based on alignment conditions, mediating between the fixed slice-based memory layout and the processing requirements, thereby achieving efficient memory access without modifying the underlying data structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Device complexity

If scanlines are processed in a fixed pattern, then processing simplicity is maintained, but view-dependent speed performance variations occur

Engineering Contradiction:
Improveprocessing pattern complexityVSAvoidspeed performance consistency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic traversal pattern selection that adapts to the alignment between volume slices and reformatting planes. When planes are aligned with slices, the system uses simple sequential traversal; when misaligned, it switches to patterns that follow slice boundaries. This dynamic adaptation maintains processing simplicity in each case while ensuring consistent performance across different viewing angles.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention applies different traversal patterns locally based on the specific alignment conditions between volume and plane. Rather than using a single complex pattern for all cases, the system selects the most appropriate simple pattern for each local situation (aligned vs. misaligned), maintaining simplicity while achieving view-independent performance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7826684B2Optimization and view dependency reduction for processing slice-based volumes
Publication Date: 2010.11.02 SIEMENS HEALTHINEERS AG
  • US7826684B2 patent drawing
  • US7826684B2 patent drawing
  • US7826684B2 patent drawing

AI summary

This invention describes an optimization and view dependency reduction method for multiplanar reformatting (MPR) of slice-based volume images. This method utilizes a traversal scheme that allows for efficient access of the computer memory layout of a sliced based volume, and therefore optimizes overall processing time. This method does not require changes to the volume memory layout or additional volume memory. Instead, efficient memory access is achieved by adaptive traversal patterns on the reformatting planes. The traversal pattern is adapted on-the-fly during rendering as the reformatting plane location and orientation is changed arbitrarily relative to the volume. In this way, the typical speed differences between various reformatting planes orientations caused by inefficient memory access is greatly reduced. Computer cache coherency, SIMD coherent implementation, and multiprocessing environments are also considered in the design of the traversal pattern.