Adaptive Verify Level Control for Non-Volatile Memory Cell Ageing

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Solution Overview

Problem

Non-volatile memory devices face challenges in maintaining accurate programming and erasing operations due to cell ageing, which leads to trap generation in the oxide, causing threshold voltage shifts and potential over-programming or over-erasing, especially in fresh or slightly aged cells, accelerating ageing and affecting data retention.

Innovation Solution

Implementing a dynamic adaptation of erase and programming verify levels based on the ageing of memory cells, using a control unit to retrieve and modify verify level values, allowing for iterative biasing configurations and pulse applications to ensure successful operations while minimizing cell degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fixed verify levels are used for programming and erasing operations, then the memory operations can be performed with simple control logic, but cell ageing causes threshold voltage shifts leading to over-programming or over-erasing especially in fresh or slightly aged cells

Engineering Contradiction:
Improveaccuracy of programming and erasing operationsVSAvoidcomplexity of verify level control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the verify levels adaptive rather than fixed. The control unit dynamically adjusts the programming verify level (PV) and erasing verify level (EV) based on the number of cycle groups completed by the memory cells. This allows the verify levels to automatically compensate for threshold voltage shifts caused by ageing, preventing over-programming or over-erasing while maintaining accurate operations throughout the memory device's lifecycle

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of verify levels from static to dynamic values. By modifying the verify level parameters based on cell ageing state (number of cycle groups), the system adapts the programming and erasing thresholds to match the current cell characteristics, thereby maintaining operational accuracy without requiring complex manual intervention

Inventive Principle:
Principle #35Parameter changes

2Reliability

If high electrical field is applied to ensure sufficient FN tunnelling effect for erase operation, then erasing effectiveness is improved, but trap generation in oxide increases causing threshold voltage shifts and accelerating cell ageing

Engineering Contradiction:
Improveeffectiveness of erase operationVSAvoidtrap generation and threshold voltage shift
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements feedback by using verify operations to check the actual state of memory cells after programming or erasing. The control unit reads the threshold voltage distribution and compares it against the target values. Based on this feedback, the system can determine whether additional cycles are needed or if the operation was successful, thereby preventing excessive field application that would cause harmful trap generation

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies preliminary action by performing verify operations after each programming or erasing cycle to check the state of cells before proceeding to the next operation. This preliminary verification allows the system to stop early if the target state is achieved, avoiding unnecessary additional cycles that would accumulate harmful traps and accelerate ageing

Inventive Principle:
Principle #10Preliminary action

3Reliability

If iterative programming or erasing cycles are performed to compensate for threshold voltage shifts, then data retention is improved, but the number of cycles increases accelerating cell ageing

Engineering Contradiction:
Improvedata retentionVSAvoidnumber of programming/erasing cycles
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent makes the number of iterative cycles dynamic rather than fixed. The control unit adapts the number of programming or erasing cycles based on the actual cell state and verify operation results. This dynamic adjustment allows the system to perform the minimum necessary cycles to achieve reliable data retention while avoiding excessive cycling that would accelerate ageing

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The feedback from verify operations enables the control unit to intelligently determine when to stop iterative cycles. By continuously monitoring the threshold voltage distribution and comparing it against target values, the system can terminate cycling early when sufficient data retention is achieved, rather than performing a fixed number of cycles that would waste time and accelerate ageing

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution optimizes memory cell ageing, improves cycling capability, and enhances data retention endurance by dynamically adjusting verify levels and biasing configurations, thereby improving the efficiency and reliability of non-volatile memory devices.

Implementation Method 1

a non-volatile memory device to be erased through the Fowler-Nordheim (FN) tunnelling effect

Methodology Applied
Scientific EffectFowler-Nordheim tunnelling effect:

Data Source

PatentUS12057180B2Non-volatile memory device with improved cell cycling and corresponding method for operating the non-volatile memory device
Publication Date: 2024.08.06 STMICROELECTRONICS SRL
  • US12057180B2 patent drawing
  • US12057180B2 patent drawing
  • US12057180B2 patent drawing

AI summary

In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.