Adaptive Verify Voltage Control for Nonvolatile Memory Cell Programming
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Solution Overview
Problem
Nonvolatile memory devices face challenges in efficiently programming multi-level cells, leading to spread threshold voltage distributions due to varying cell speeds, which affects data retention and integration density.
Innovation Solution
The nonvolatile memory device employs a method where a first verify voltage is applied in a first program loop, and based on the verification results, a second verify voltage is adjusted as an offset point in a subsequent program loop, reducing the verify voltage to narrow the threshold voltage distribution and prevent over-programming of high cell-speed memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single verify voltage is used for all memory cells in multi-level cell programming, then the programming process is simple, but the threshold voltage distribution spreads due to varying cell speeds
Solution Approach 1:
The patent applies dynamics by making the verify voltage adaptive rather than static. The verify voltage is dynamically adjusted based on the program loop number and verification results, allowing the system to adapt to varying cell speeds during programming. This resolves the contradiction by introducing dynamic voltage adjustment that narrows threshold voltage distribution without significantly increasing overall system complexity.
Solution Approach 2:
The patent changes the verify voltage parameter during the programming process. Different verify voltages are applied in different program loops, with the voltage level adjusted based on the current loop number and verification outcomes. This parameter change strategy allows the system to accommodate cell speed variations and narrow threshold voltage distribution while maintaining a relatively simple programming framework.
2Reliability
If programming continues until all cells are fully programmed, then data retention is improved, but high cell-speed cells become over-programmed causing threshold voltage spread
Solution Approach 1:
The patent implements feedback by continuously monitoring verification results during the programming process. Based on the verification outcomes in each program loop, the system adjusts the verify voltage and determines whether to continue programming. This feedback mechanism ensures that programming stops at the appropriate point for each cell, preventing over-programming of fast cells while ensuring sufficient programming for slow cells, thus maintaining data retention without excessive threshold voltage spread.
Solution Approach 2:
The patent applies partial action by programming cells to different extents based on their individual characteristics. Instead of uniformly programming all cells to the same level, the system applies programming selectively - some cells receive full programming while others receive partial programming sufficient for their speed characteristics. This prevents over-programming while ensuring adequate programming for data retention.
3Manufacturing precision
If verify voltage is adjusted frequently to narrow threshold voltage distribution, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the programming process into multiple discrete program loops, with each loop using a specific verify voltage level. The verify voltage is adjusted at defined segments (program loops) rather than continuously, which narrows threshold voltage distribution while keeping control complexity manageable. This segmented approach balances precision improvement with acceptable device complexity.
Data Source
AI summary
A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.