Adaptive Via Footprint Adjustment for Panelized Semiconductor Packaging

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Solution Overview

Problem

In semiconductor device manufacturing, panelized packaging processes often result in misalignment of semiconductor die during the overmolding and mounting processes, leading to defective packages and increased yield loss due to the displacement and rotation of semiconductor die, which affects the quality and reliability of the final product.

Innovation Solution

The method involves forming a panel with an encapsulating material around semiconductor die, measuring their actual positions, and adjusting the nominal footprint of conductive vias to account for misalignment by forming capture pads and modifying the shape or size of the vias to ensure proper alignment and connection, even when the die are not in their nominal positions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If panelized packaging processes are used to increase productivity, then manufacturing efficiency is improved, but misalignment of semiconductor die occurs leading to decreased manufacturing precision

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidalignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming capture pads and adjusting via footprints before the actual die placement and overmolding processes. The nominal footprint of conductive vias is modified in advance to account for expected misalignment, and capture pads are positioned to accommodate die displacement. This preparatory configuration enables the process to tolerate alignment variations while maintaining connection reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes geometric parameters of the conductive vias by adjusting their nominal footprint to create modified footprints with larger dimensions. This parameter modification allows the vias to compensate for die misalignment by providing a larger target area for electrical connections, thereby maintaining manufacturing precision despite variations in die positioning during panelized packaging.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If smaller bond pad openings are used to increase packaging density, then area is reduced, but alignment tolerance decreases leading to increased defect rate

Engineering Contradiction:
Improvepackage footprintVSAvoidconnection reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by creating non-uniform via footprints where the conductive via structure has enlarged dimensions specifically at the connection interface with the bond pad. The modified via footprint provides localized area expansion at the critical connection point while maintaining smaller overall package dimensions, thus simultaneously achieving high density and reliable connections.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If adaptive patterning with dynamic via clipping is implemented to improve alignment, then manufacturing complexity increases, but yield is improved

Engineering Contradiction:
Improvevia-to-pad alignmentVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The adaptive patterning process uses preliminary action by pre-calculating and pre-adjusting the via footprint dimensions based on expected misalignment scenarios. The nominal footprint is modified in advance to create a robust design that accommodates variation, eliminating the need for complex real-time adjustments during manufacturing while maintaining high alignment precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9978655B2Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping
Publication Date: 2018.05.22 DECA TECH USA INC
  • US9978655B2 patent drawing
  • US9978655B2 patent drawing
  • US9978655B2 patent drawing

AI summary

A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline.