Adaptive Voltage Control for Nonvolatile Memory Erase Degradation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices with vertically stacked memory cells face challenges in maintaining data erase characteristics over cycles, leading to degraded performance and reduced reliability.
Innovation Solution
A method and device that determine the degradation of data erase characteristics for each predetermined cycle, adjusting either the voltage level or application time of selection transistors to improve data erase operations, thereby enhancing the reliability and longevity of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data erase operation is performed repeatedly in nonvolatile memory device, then data erase characteristic degrades, but maintaining original voltage and time parameters cannot restore performance
Solution Approach 1:
The patent applies dynamics by making the voltage level and application time of selection transistors adjustable parameters that change based on degradation detection. Instead of fixed parameters, the system dynamically adapts voltage and time values to compensate for wear, allowing the erase operation to maintain effectiveness throughout the device lifetime.
Solution Approach 2:
The patent directly implements parameter changes by modifying voltage level and application time parameters of selection transistors based on detected degradation. The control circuit adjusts these parameters upward when degradation is detected, changing the physical operating conditions to compensate for wear and maintain erase characteristic.
2Reliability
If voltage level or application time is increased to compensate for degradation, then data erase characteristic is restored, but energy consumption increases
Solution Approach 1:
The patent implements feedback by detecting data erase characteristic degradation and using this information to adjust voltage and time parameters. The control circuit continuously monitors erase performance and adjusts parameters accordingly, creating a closed-loop system that optimizes energy usage by only increasing power when necessary to maintain performance.
3Reliability
If adaptive voltage and time adjustment is implemented, then reliability and lifetime are improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling the memory device to automatically detect its own degradation and adjust its operating parameters without external intervention. The control circuit monitors erase characteristic and autonomously modifies voltage and time parameters, allowing the device to self-correct performance issues.
Data Source
AI summary
In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.