Adaptive Voltage Distribution for Multi-Plane NAND Flash Programming
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Solution Overview
Problem
In NAND flash memory systems, adaptive programming voltage (VPGM) is insufficient for new blocks with fewer program-erase cycles, leading to under-programming, while existing blocks may be over-programmed, resulting in inefficiencies in multi-plane programming operations.
Innovation Solution
Applying a delta voltage based on the number of program-erase cycles to the programming voltage across shared programming lines, allowing new blocks to receive sufficient voltage while preventing over-programming of existing blocks by adjusting bit line voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If adaptive programming voltage is applied to compensate for increased programming speed in blocks with high P/E cycles, then existing blocks are properly programmed, but new blocks with fewer P/E cycles receive insufficient voltage and become under-programmed
Solution Approach 1:
The patent applies different voltage adjustments to different blocks based on their individual P/E cycle counts. Blocks with higher P/E cycles receive a reference programming voltage, while blocks with fewer P/E cycles receive an increased voltage (reference voltage plus delta voltage). This local differentiation ensures each block receives the appropriate voltage for its wear state, resolving the contradiction between reliability for worn blocks and precision for new blocks.
Solution Approach 2:
The patent dynamically adjusts the programming voltage based on the P/E cycle count of each block. The controller determines the P/E cycle count and selectively applies voltage adjustments during multi-plane programming operations. This dynamic adaptation allows the system to optimize programming voltage in real-time based on block wear state, ensuring both reliability for existing blocks and proper programming for new blocks.
2Ease of operation
If a single programming voltage is applied to all blocks in multi-plane programming, then programming operation is simplified, but blocks with different P/E cycles experience either over-programming or under-programming
Solution Approach 1:
The patent changes the voltage parameter based on the P/E cycle count of each block. During multi-plane programming, the controller identifies blocks with fewer P/E cycles and applies an increased voltage (reference voltage plus delta voltage) to those specific blocks, while maintaining the reference voltage for blocks with higher P/E cycles. This parameter adjustment ensures programming reliability across blocks with different wear states while maintaining operational simplicity through automated voltage selection.
3Manufacturing precision
If additional programming pulses are applied to new blocks to ensure proper programming, then new blocks are properly programmed, but programming time and efficiency increase
Solution Approach 1:
The patent applies the voltage adjustment based on P/E cycle count before the actual programming operation begins. The controller determines which blocks require increased voltage and pre-configures the programming voltage for each block. This preliminary action ensures that new blocks receive sufficient voltage from the first programming pulse, eliminating the need for additional programming loops and verify-fail-retry cycles, thereby reducing programming time while ensuring completeness.
Data Source
AI summary
Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks. In this manner, the same programming voltage is applied to planes in a multi-plane programming operation, and the existing blocks receive a relatively lower gate-to-channel voltage, while the new block(s) receive a relatively higher gate-to-channel voltage.