Adaptive Voltage Scaling with Critical Path Monitors
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Solution Overview
Problem
Integrated circuits face challenges in minimizing power consumption while maintaining performance, as lowering the input voltage reduces power consumption but can lead to operational faults and performance degradation.
Innovation Solution
The implementation of a closed-loop adaptive voltage scaling system with critical path monitors and envelope circuits that allow the integrated circuit to operate in mixed modes, enabling dynamic voltage adjustment based on performance feedback and calibration tests to set optimal voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input voltage level for IC components is lowered to reduce power consumption, then power consumption decreases, but performance level and operational reliability deteriorate
Solution Approach 1:
The patent implements dynamic voltage adjustment through a closed-loop control system that continuously monitors IC performance and adapts the voltage level in real-time. The system transitions from static voltage provisioning to dynamic voltage scaling, allowing the voltage to be adjusted based on actual operational conditions, process variations, and temperature, thereby maintaining reliability while optimizing power consumption.
Solution Approach 2:
The patent employs a closed-loop feedback mechanism where performance monitors continuously measure IC operation quality and feed this information back to the voltage control system. This feedback enables the system to detect performance degradation trends and adjust voltage levels proactively, preventing operational faults while minimizing power consumption through optimal voltage provisioning.
2Use of energy by moving object
If the input voltage level for IC components is lowered to reduce power consumption, then power consumption decreases, but performance level deteriorates
Solution Approach 1:
The system dynamically adjusts voltage based on actual performance requirements rather than using a fixed low voltage. By implementing adaptive voltage scaling with real-time monitoring, the system can temporarily increase voltage to meet performance demands while maintaining lower average power consumption, thus resolving the contradiction between power efficiency and productivity.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on multiple factors including process variations, temperature, and performance requirements. This parameter adaptation allows the system to optimize the voltage level for each operating condition, achieving lower power consumption without sacrificing performance when high productivity is needed.
3Reliability
If voltage is adjusted to account for process variations and temperature, then operational faults are prevented, but system complexity increases
Solution Approach 1:
The patent implements a self-service approach where the IC device autonomously monitors its own performance and automatically adjusts its voltage level without external intervention. The built-in performance monitors and control logic enable the system to self-regulate, compensating for process variations and temperature effects while minimizing the need for complex external control infrastructure.
Solution Approach 2:
The patent designs a universal control architecture that handles multiple functions including performance monitoring, voltage adjustment, and fault prevention through a single integrated system. This multi-functional approach reduces overall system complexity by consolidating control functions rather than requiring separate mechanisms for each function.
Data Source
AI summary
In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.