Adaptive Wafer Electrical Testing via Inline Data
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Solution Overview
Problem
Current electrical testing methods for wafers are inefficient as they do not effectively utilize inline wafer-related data to adapt testing strategies, leading to increased test time and costs, and lack the granularity to accurately localize failures within device circuitry.
Innovation Solution
A computer-implemented method that determines electrical test paths and parameters based on inline defect and metrology data, allowing for dynamic rearrangement of test sequences to quickly identify defective dies and reduce testing costs, by correlating physical attributes of test paths with inline data for real-time decision-making.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed test plans are used, then test coverage is comprehensive, but test time is excessive and costs increase
Solution Approach 1:
The patent implements dynamic test plan selection that adapts to real-time wafer conditions. Instead of using fixed test plans, the system continuously monitors inline data (defect rates, metrology shifts) and dynamically adjusts the test plan intensity and type. This allows the system to reduce test time when wafers are good while maintaining comprehensive coverage when defects are detected, resolving the contradiction between comprehensive coverage and excessive test time.
Solution Approach 2:
The system changes test parameters (number of test vectors, test intensity, test plan selection) based on inline wafer data. When inline data shows low defect rates, the system reduces test parameters to save time. When inline data indicates high defect rates or metrology shifts, the system increases test parameters to maintain comprehensive coverage. This dynamic parameter adjustment resolves the contradiction between thorough testing and time efficiency.
2Loss of information
If debug test plans with large number of test vectors are used, then failure localization capability is improved, but test time and costs increase significantly
Solution Approach 1:
The patent applies partial action by selecting only the necessary portion of debug test vectors based on inline data. Instead of always applying the full debug test plan with all test vectors, the system uses inline defect data to identify which specific test vectors are needed for failure localization. This partial application of debug testing maintains failure localization capability while significantly reducing test time when full debug testing is not required.
Solution Approach 2:
The system applies local quality by targeting specific test vectors based on inline defect locations and characteristics. Rather than uniformly applying comprehensive debug testing across all dies, the system localizes the testing effort to areas where failures are most likely to occur based on inline data analysis. This targeted approach maintains effective failure localization while reducing overall test time and costs.
3Loss of time
If pass/fail test plans with stop on first fail are used, then test time per die is reduced, but ability to localize failures is lost
Solution Approach 1:
The patent implements feedback by using inline wafer data (defect rates, metrology shifts) to guide test plan selection. The system continuously monitors inline process data and feeds this information back to dynamically adjust the test plan. When inline data indicates good wafer quality, the system uses quick pass/fail testing. When inline data indicates potential problems, the system automatically transitions to more informative debug testing. This feedback mechanism ensures failure localization information is obtained precisely when needed, without unnecessarily increasing test time for good wafers.
4Adaptability or versatility
If manual engineering judgment is used to select test plans, then flexibility is achieved, but productivity and consistency are reduced
Solution Approach 1:
The patent implements self-service by enabling the test system to automatically select and adjust test plans based on inline wafer data without requiring manual engineering intervention. The system autonomously monitors inline process data, analyzes wafer quality indicators, and dynamically selects appropriate test plans. This automation maintains the flexibility of expert engineering judgment while dramatically improving productivity by eliminating manual decision-making bottlenecks and ensuring consistent, repeatable test plan selection across all wafers.
Data Source
AI summary
A method and a system for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information.