Adaptive Wear Leveling for Nonvolatile Memory Blocks

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Solution Overview

Problem

Conventional wear management routines in semiconductor memory devices result in significant operational overhead and fail to adequately manage wear, leading to degraded performance and reduced endurance due to uneven erase operations across memory blocks.

Innovation Solution

A semiconductor memory device with a nonvolatile memory and a memory controller that executes a wear leveling method by detecting and comparing erase counts, swapping data between blocks, and adjusting the frequency of wear leveling operations based on a reference count to balance wear across memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional wear management routines are executed frequently to manage wear across memory blocks, then wear leveling is improved, but operational overhead increases significantly

Engineering Contradiction:
Improvewear levelingVSAvoidoperational overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the wear leveling execution rate adaptive rather than fixed. The memory controller dynamically adjusts the wear leveling execution rate based on real-time wear detection, transitioning from infrequent executions during low-wear periods to more frequent executions during high-wear periods, thereby optimizing the balance between reliability and productivity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of wear leveling execution rate from a static constant to a dynamic variable. By detecting wear levels and adjusting the execution rate accordingly, the system optimizes performance based on actual wear conditions, reducing unnecessary operations during low-wear states while maintaining protection during high-wear states

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional wear management routines operate independently of I/O operations, then wear management can be performed, but memory performance degrades and actual wear is not adequately managed

Engineering Contradiction:
Improvewear managementVSAvoidmemory performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements feedback by detecting actual wear levels resulting from I/O operations and using this information to adjust wear management actions. The system monitors wear detection results and adapts its behavior accordingly, creating a closed-loop control system that responds to actual wear conditions rather than operating independently

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-service by automatically detecting wear levels and adjusting wear management execution based on actual conditions. The memory controller monitors its own wear state and autonomously determines when wear leveling should be executed, eliminating the need for external intervention and optimizing performance based on real-time conditions

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8209468B2Semiconductor memory device and wear leveling method
Publication Date: 2012.06.26 SAMSUNG ELECTRONICS CO LTD
  • US8209468B2 patent drawing
  • US8209468B2 patent drawing
  • US8209468B2 patent drawing

AI summary

Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The memory controller adjusts a period of managing the wear leveling with reference to the erasing counts.