Analog Neural Memory Array With Adaptive Weight Mapping and Stable Impedance
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Solution Overview
Problem
Existing analog neural memory arrays face challenges with varying source impedance and power consumption across cells, leading to precision and noise issues during read, program, or erase operations.
Innovation Solution
The implementation of an analog neural memory system with non-volatile memory cells arranged in rows and columns, where each memory cell has a constant source impedance and power consumption, achieved through the use of dummy bit lines and bit line transistors to maintain consistent impedance and power usage across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog neural memory arrays are used, then the array can perform neural network computations, but the source impedance varies across cells leading to precision and noise issues
Solution Approach 1:
The patent applies equipotentiality by introducing dummy bit lines connected to all memory cells through bit line transistors. These dummy bit lines are maintained at a constant potential (ground or reference voltage) to ensure that all memory cells experience the same source impedance during read operations, regardless of their physical location in the array. This eliminates the impedance variation that causes precision and noise issues.
Solution Approach 2:
The patent uses bit line transistors as intermediary elements between the memory cells and the actual bit lines. These transistors act as mediators that buffer and isolate the impedance effects, ensuring that variations in memory cell impedance do not propagate to the read circuitry. The dummy bit lines serve as additional intermediary pathways that stabilize the overall source impedance.
2Measurement precision
If conventional analog neural memory arrays are used, then the array can perform neural network computations, but power consumption varies across bit lines leading to noise and precision issues
Solution Approach 1:
The dummy bit lines are maintained at a constant potential and connected to all memory cells, creating an equipotential reference that stabilizes power distribution. This ensures that power consumption is evenly distributed across all bit lines during read operations, preventing localized power variations that would cause noise and precision degradation.
Solution Approach 2:
The patent creates homogeneous power distribution by connecting all memory cells to dummy bit lines through identical bit line transistors. This homogeneous configuration ensures that each memory cell draws power under the same conditions, eliminating the heterogeneous power consumption patterns that lead to noise and precision issues in conventional arrays.
3Productivity
If non-volatile memory cells are used for analog neural networks, then high connectivity and parallelism can be achieved, but source impedance and power consumption vary across the array
Solution Approach 1:
The patent segments the bit line interface by introducing separate dummy bit lines for each memory cell column. This segmentation allows independent control and stabilization of impedance for each segment of the array, enabling high parallelism while maintaining consistent impedance across all segments through individual bit line transistor control.
Solution Approach 2:
The dummy bit lines serve multiple functions simultaneously: they provide impedance stabilization, power consumption equalization, and signal reference for all memory cells. This multi-functionality allows the array to maintain high computational parallelism while ensuring reliability through consistent impedance and power distribution across all operational units.
Data Source
AI summary
Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.