Adaptive Word Line Stress for NAND Leakage Detection
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in detecting word line shorts and leaks, which can lead to defects and data loss, and current testing methods during program operations impact performance.
Innovation Solution
A self-adaptive word line leakage test is implemented, where higher leakage devices receive more stress, and lower leakage devices receive less stress, by applying a high voltage to stress-selected word lines and monitoring current draw to detect and differentiate leakage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high voltage is applied to stress-selected word lines to detect leakage, then leakage detection capability is improved, but device complexity increases due to additional testing circuitry and control mechanisms
Solution Approach 1:
The control circuit is designed to perform multiple functions: it applies stress voltages to selected word lines for leakage detection, monitors current draw through existing bit line interfaces, and integrates with standard program/verify operations. This multi-functionality improves leakage detection capability while minimizing additional circuitry complexity by reusing existing memory structure components.
Solution Approach 2:
The memory structure uses its own existing components (bit lines, word lines, NAND strings) to perform leakage detection without requiring entirely separate testing equipment. The current draw monitoring leverages the natural electrical characteristics of the memory cells themselves, allowing the device to self-diagnose leakage conditions using integrated resources rather than external complex testing apparatus.
2Reliability
If testing for defects during program operations is implemented, then defect detection is improved, but performance deteriorates due to additional testing overhead
Solution Approach 1:
The leakage detection operation is merged with the existing program/verify sequence by applying stress voltages during idle periods or overlapping with verify operations. The control circuit combines leakage monitoring with standard program operations, so that defect detection occurs concurrently with normal memory functions rather than as a separate sequential step, thereby improving reliability without proportionally increasing testing overhead.
Solution Approach 2:
Rather than continuously monitoring during every program operation, the system implements periodic leakage checks at strategically chosen intervals within the program/verify sequence. This periodic approach maintains adequate defect detection capability while reducing the overall testing overhead and preserving program operation performance by allowing normal operations to proceed between check points.
3Productivity
If adaptive stress levels are applied based on leakage severity, then device yield is improved, but control complexity increases due to dynamic stress adjustment mechanisms
Solution Approach 1:
The control circuit dynamically adjusts stress voltage levels based on real-time current draw measurements from different word lines. Word lines exhibiting higher leakage currents receive higher stress voltages to fully characterize and identify defects, while word lines with lower leakage receive proportionally lower stress. This dynamic adaptation improves device yield by accurately distinguishing between defective and functional word lines without applying excessive stress that could damage good cells, achieving differentiated stress control through relatively simple current monitoring and voltage adjustment logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively identifies and differentiates word line leaks, minimizing defects and improving device yield by optimizing stress levels based on leakage severity.
Implementation Method 1
A self-adaptive word line leakage test is implemented, where higher leakage devices receive more stress, and lower leakage devices receive less stress, by applying a high voltage to stress-selected word lines
Implementation Method 2
monitoring current draw to detect and differentiate leakage levels
Data Source
AI summary
In a word line leakage detection process in a NAND or other non-volatile memory device, a stress selected set of word lines have a high stress voltage applied while other parts of an array are biased to a low level. While stressing the memory array, the current drawn by the array is compared to a leakage detection current that increases in amplitude. For example, this can be done by mirroring the array current and comparing this with the current from a current source that increases in response to a digital input value and determining when it exceeds the mirror current, at which point the stress is discontinued. In addition to determining the amount of leakage, this approach results in low leakage word lines receiving less stress, while greater leakage result in greater amounts of stress being applied.