Adaptive Word Line Read Timing for Cycling-Aware NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory technologies face limitations in read performance due to variations in threshold voltage (Vth) caused by the coupled-up state of word lines, leading to issues like read disturb and inefficient read operations.
Innovation Solution
The implementation of a memory apparatus and method that adjusts word line read timing and ramping parameters based on the cycling history of memory cells, using a controller to optimize read operations and mitigate Vth shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If word line read timing and ramping parameters are adjusted to improve read performance, then read speed and efficiency are improved, but read disturb and reliability deteriorate
Solution Approach 1:
The patent applies dynamics by making the word line read timing and ramping parameters adjustable and adaptive rather than fixed. The control circuit dynamically modifies these parameters based on the coupled-up state of word lines, allowing the system to optimize read speed while preventing read disturb through real-time parameter adjustment.
Solution Approach 2:
The patent implements parameter changes by modifying word line read timing and ramping parameters according to the cycling history and coupled-up state of memory cells. The control circuit changes these electrical parameters to stabilize threshold voltage variations and improve read performance while maintaining reliability.
2Reliability
If fixed word line read parameters are used to prevent read disturb, then reliability is maintained, but read performance and speed deteriorate
Solution Approach 1:
The system transitions from static fixed parameters to dynamic adjustable parameters. The control circuit enables real-time modification of word line read timing and ramping parameters based on the actual state of memory cells, allowing the system to maintain reliability while optimizing read performance according to cycling history.
Solution Approach 2:
The patent implements feedback by having the control circuit monitor the coupled-up state of word lines and adjust read parameters accordingly. This feedback mechanism allows the system to maintain reliability by detecting conditions that may cause read disturb while simultaneously optimizing read performance through adaptive parameter adjustment.
3Measurement precision
If word lines are kept at elevated voltage to improve read margin, then read accuracy is improved, but threshold voltage shifts and read disturb increase
Solution Approach 1:
The patent applies parameter changes by adjusting word line read timing and ramping parameters based on the coupled-up state and cycling history. This dynamic parameter adjustment allows the system to maintain adequate read margin while preventing excessive threshold voltage shifts and read disturb that would result from fixed elevated voltage conditions.
Solution Approach 2:
The patent implements preliminary action by having the control circuit determine the coupled-up state of word lines before executing the read operation. Based on this preliminary assessment, the system pre-adjusts the read parameters to optimize read margin while preventing threshold voltage shifts, rather than using fixed parameters regardless of the actual state.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.