Adaptive Wordline Refresh Logic Circuitry for Memory Power Management
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Solution Overview
Problem
The increasing demand for high-performance computational workloads, particularly in artificial intelligence and virtual-reality graphics, poses challenges for memory systems due to higher latency and power consumption issues, especially when using Compute Express Link (CXL) devices.
Innovation Solution
The implementation of adaptive wordline refresh logic circuitry in memory arrays, which staggers the activation of multiple wordlines during refresh operations, reducing peak current draw and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple wordlines are activated simultaneously during refresh operations, then refresh efficiency is improved, but peak power consumption increases
Solution Approach 1:
The patent segments the wordline activation process by dividing multiple wordlines into different groups that are activated at different times. The logic circuitry selectively delays activation signals for second groups of wordlines relative to first groups, creating a temporal segmentation that reduces peak power consumption while maintaining refresh coverage.
Solution Approach 2:
The patent introduces dynamic control of wordline activation timing through logic circuitry that can selectively delay activation signals based on operational conditions. This dynamic adjustment allows the system to optimize between refresh efficiency and power consumption by adapting the activation schedule to current operational requirements.
2Quantity of substance
If more memory capacity is provided to meet increasing data set requirements, then application performance is improved, but power consumption and latency increase
Solution Approach 1:
The patent segments the memory refresh operation into multiple phased activations of wordline groups. This segmentation allows large memory capacities to be refreshed in controlled stages rather than all at once, reducing the peak power consumption associated with refreshing large memory structures while maintaining the required memory capacity.
Data Source
AI summary
Described apparatuses and methods relate to adaptive wordline refresh for a memory system that may support a nondeterministic protocol. To help manage power delivery networks in a memory system, a memory device can include logic that can stagger activation of multiple wordlines that are to be activated or refreshed approximately simultaneously. The logic circuitry can be coupled between wordlines that are to be activated and delay propagation of the activation signal. Thus, a first group of wordlines (e.g., “before” the logic circuitry) are activated by the signal, but activation of a second group of wordlines (e.g., “after” the logic circuitry), is delayed, reducing the peak current draw. Additional logic circuitries can be coupled between the wordlines to divide the wordlines into multiple groups, thereby staggering the activation of wordlines that are activated by a refresh command, which can reduce the peak current draw and power consumption.