Adaptive Write Word Line Pulse Control for Memory Reliability
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Solution Overview
Problem
As process geometries shrink in modern data processing systems, the variability in memory cell operating characteristics increases, leading to challenges in determining the appropriate write word line pulse width for memory devices, resulting in write failures or reduced operation frequency, especially at lower supply voltages.
Innovation Solution
A memory device with adaptive write word line pulse width control, where comparing circuitry monitors the data stored in addressed memory cells and de-asserts the write word line signal once a match is detected, ensuring the pulse width is only as long as necessary for the actual memory cells being written, reducing unnecessary margin and minimizing data corruption in half-selected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write word line pulse width is increased to accommodate worst case memory cells, then write operation reliability is improved, but the operation frequency is reduced
Solution Approach 1:
The patent applies dynamics by making the write word line pulse width adaptive rather than fixed. The pulse width is dynamically adjusted based on the actual write completion status of memory cells, allowing the system to optimize between reliability and speed for each specific write operation rather than using a conservative fixed width that limits overall frequency.
Solution Approach 2:
The patent implements feedback by monitoring the actual write completion status of memory cells and using this information to control the pulse width. The system waits for write completion detection before de-asserting the word line signal, creating a closed-loop control mechanism that ensures reliability while minimizing unnecessary pulse duration.
2Reliability
If the write word line pulse width is increased to ensure worst case memory cell operation, then write failures are prevented, but the margin for process variability is increased
Solution Approach 1:
The patent applies self-service by having the memory cell write operation itself determine when it is complete, eliminating the need for external conservative margin calculations. The system uses the actual physical completion state of the write operation to control the pulse width, allowing the process to self-regulate rather than relying on pre-calculated safety margins.
3Speed
If word line voltage is increased to reduce margin requirements, then operating speed is improved, but data corruption in half-selected cells occurs
Solution Approach 1:
The patent applies dynamics by making the word line signal assertion duration adaptive. Instead of using a fixed long pulse width that causes half-select problems, the system dynamically extends the pulse only as long as necessary for the actual write operation to complete, thereby maintaining speed benefits while eliminating data corruption in non-addressed cells.
Data Source
AI summary
A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques.