Adaptive Write Timing Circuits for 3DXP Memory Devices
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Solution Overview
Problem
Three-dimensional crosspoint memory (3DXP) devices face inefficiencies in write operations due to varying transmission line propagation times and the need for frequent profile switching, leading to increased storage requirements and reduced write efficiency as the number of devices increases.
Innovation Solution
Implementing adaptive write timing circuits within each 3DXP device to derive and store custom timing settings, allowing them to adjust their write timing independently, reducing the reliance on external memory controller profiles and minimizing profile switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple 3DXP devices are connected via a common bus, then data transmission capability is improved, but profile switching time increases reducing write efficiency
Solution Approach 1:
Each 3DXP device autonomously derives and stores its own custom timing settings through adaptive write timing circuits, eliminating the need for external memory controller profiles. This self-service approach allows devices to independently optimize their timing parameters without requiring profile switching, thereby maintaining high write efficiency while enabling multiple devices to share a common bus.
Solution Approach 2:
The timing optimization function is segmented from the memory controller and distributed to individual 3DXP devices. Each device maintains its own timing settings locally, allowing parallel operation without centralized coordination. This segmentation eliminates the bottleneck of profile switching while preserving the ability to support multiple devices on the common bus.
2Measurement precision
If custom timing settings are stored externally in memory controller, then write accuracy is improved, but storage requirements increase
Solution Approach 1:
The timing settings are transitioned from external storage in the memory controller to internal storage within each 3DXP device. This dimensional shift moves the storage responsibility from the controller's memory resources to the individual devices' local memory, eliminating the need for extensive external storage while maintaining precise timing control for accurate writes.
Solution Approach 2:
Each 3DXP device independently stores and manages its own timing settings, eliminating the need for the memory controller to allocate storage resources for multiple devices' profiles. This self-service storage approach reduces overall system storage requirements while preserving write accuracy through device-specific timing optimization.
3Adaptability or versatility
If frequent profile switching is performed, then adaptability to different devices is improved, but write efficiency decreases
Solution Approach 1:
Each 3DXP device pre-derives and stores its custom timing settings during an initial adaptive training phase. This preliminary action eliminates the need for repeated profile switching during normal operation, as devices are pre-configured with their optimal timing parameters. The result is maintained device adaptability without the productivity loss from frequent switching.
Solution Approach 2:
Devices autonomously determine and store their own timing characteristics during adaptive training, eliminating the need for the memory controller to manage and switch between multiple profiles. This self-service adaptability mechanism maintains high device-specific optimization while achieving efficient parallel operation across multiple devices.
Data Source
AI summary
A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a write training setting configured to adjust a write timing of data being sent by the memory controller to the one or more memory devices during write operations of the memory system.