Adaptively Biased Gate Shield for LDMOS Trade-offs
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Solution Overview
Problem
Semiconductor power devices face a trade-off between breakdown voltage and on-state resistance, where increasing breakdown voltage leads to higher on-state resistance, making it difficult to efficiently handle high currents without excessive power consumption and heat generation.
Innovation Solution
The use of an adaptively biased gate shield in LDFET transistors, which applies a variable voltage based on the device's state to separately manage breakdown voltage and on-state resistance, allowing for increased breakdown voltage while maintaining low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the breakdown voltage is increased to handle high voltages, then the device can withstand higher voltages, but the on-state resistance increases leading to higher power consumption and heat generation
Solution Approach 1:
The gate shield is biased with a variable voltage that dynamically changes based on the device state. During the off-state, the gate shield is biased at a higher voltage to enhance breakdown voltage and withstand capability. During the on-state, the gate shield voltage is reduced to lower the on-state resistance and minimize power consumption. This dynamic voltage adjustment resolves the contradiction between high breakdown voltage and low power consumption.
Solution Approach 2:
The invention changes the voltage parameter of the gate shield based on operational state. By adjusting the gate shield voltage from a higher value during off-state to a lower value during on-state, the device optimizes both breakdown voltage and on-state resistance characteristics, thereby resolving the trade-off between voltage withstanding capability and power consumption.
2Use of energy by moving object
If the LDD region is heavily doped to reduce on-state resistance, then power consumption decreases, but the breakdown voltage and punch-through resistance are compromised
Solution Approach 1:
Instead of using a fixed heavy doping in the LDD region, the invention dynamically adjusts the effective doping through variable gate shield biasing. During off-state, the higher gate shield voltage provides enhanced field control and breakdown voltage. During on-state, the reduced gate shield voltage allows the LDD region to function with lower effective resistance. This dynamic approach allows the device to achieve low power consumption without permanently compromising breakdown voltage.
Solution Approach 2:
The gate shield acts as an intermediary element that mediates between the conflicting requirements of high breakdown voltage and low on-state resistance. By controlling the electric field distribution through variable gate shield biasing, it enables the LDD region to provide low resistance during on-state while maintaining adequate breakdown voltage during off-state, thus resolving the contradiction.
3Strength
If a gate shield is used to block large current and voltage signals, then the gate-to-drain capacitance is reduced and breakdown voltage is improved, but the on-state resistance increases
Solution Approach 1:
The gate shield voltage is made dynamic rather than fixed. During off-state, the gate shield is biased at a higher voltage to provide strong shielding and enhance breakdown voltage. During on-state, the gate shield voltage is reduced to minimize its blocking effect and lower the on-state resistance. This dynamic voltage control resolves the contradiction between using a gate shield for breakdown voltage improvement and avoiding excessive on-state resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decouples breakdown voltage and on-state resistance, enabling semiconductor power devices to handle high voltages and currents with reduced power consumption and heat generation by dynamically adjusting the effective dopant concentration of the LDD region.
Implementation Method 1
The control circuit applies a variable voltage to the shield plate that: (1) pulls majority carriers in the first doped drain region towards the shield plate before the transistor is switched on
Implementation Method 2
pushes majority carriers in the first doped drain region away from the shield plate before the transistor is switched off
Data Source
AI summary
An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.