ADC Control Circuit with Adjustable Capacitance for Low Quiescent Current
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Solution Overview
Problem
In voltage regulators and switching power supplies, the quiescent current consumption is high during low load conditions, leading to inefficiencies, and existing solutions like pulse frequency modulation and smart power management do not adequately address the reduction of quiescent currents.
Innovation Solution
A circuit and method utilizing a successive approximation register and an adjustable capacitor, with a comparator, that switches between operating modes to control output voltage, where the successive approximation register is active in high-load modes and the comparator takes over in low-load modes, reducing quiescent current by adjusting capacitance and powering down unnecessary components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the successive approximation register is used for voltage control, then the voltage regulation precision is improved, but the quiescent current consumption increases at low load conditions
Solution Approach 1:
The patent applies dynamics by making the control architecture adaptable between two operating modes. The system dynamically switches between SAR mode (for high precision voltage regulation) and PFM mode (for low power consumption), allowing the quiescent current to be reduced at low load conditions while maintaining precision when needed. This is achieved through mode detection circuitry that monitors load conditions and transitions the control mechanism accordingly.
Solution Approach 2:
The patent changes the operational parameters of the ADC and control circuit by switching between two distinct operating modes. In the first mode, the SAR ADC operates with full precision for accurate voltage regulation. In the second mode, the system transitions to PFM operation with reduced switching frequency and lower quiescent current. This parameter change allows the system to optimize between precision and power consumption based on load conditions.
2Speed
If the switching frequency is increased to improve voltage regulation response, then the regulation speed is improved, but the quiescent current losses increase
Solution Approach 1:
The patent employs periodic action through pulse frequency modulation (PFM) in the second operating mode. Instead of continuous high-frequency switching, the system uses periodic switching with variable frequency and duty cycle. This allows the regulation speed to be maintained when necessary while reducing the average quiescent current losses during light load conditions, as the switching operations are performed only when needed to maintain voltage regulation.
3Measurement precision
If additional components like resistive dividers are added to improve voltage feedback accuracy, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent applies universality by making the ADC and control circuit perform multiple functions. The same SAR ADC and control logic are used for both precise voltage measurement and for controlling the power stage in both SAR and PFM modes. This multi-functionality eliminates the need for separate resistive divider networks and additional feedback components, thereby maintaining measurement precision while reducing device complexity.
Solution Approach 2:
The patent merges the voltage feedback function with the ADC measurement function. Instead of using separate resistive dividers for voltage scaling and feedback, the system combines these functions into the ADC's reference voltage and feedback path. The ADC directly measures the feedback voltage without requiring external resistive divider networks, thus improving feedback accuracy while reducing the number of additional components needed.
Data Source
AI summary
A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.