ADC Alias Rejection Using Split-Rate Sampling Architecture
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) circuits face challenges in effectively rejecting aliasing while managing power consumption, as conventional methods either require expensive anti-aliasing filters or operate at higher sampling rates across the entire circuit.
Innovation Solution
The proposed solution involves designing ADC circuits with integrated aliasing rejection, where only a portion of the circuit operates at a higher sampling rate than the rest, utilizing techniques such as pipelined ADCs and successive-approximation register (SAR) ADCs with multi-input comparators and capacitive digital-to-analog converters (CDACs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire ADC circuit operates at a higher sampling rate to reject aliasing, then aliasing rejection is improved, but power consumption increases
Solution Approach 1:
The ADC circuit is divided into two portions: a first portion (e.g., SAR ADC or filter stages) operating at the base sampling rate and a second portion (e.g., flash ADC or sampling switches) operating at a higher sampling rate. This segmentation allows aliasing rejection functionality to be concentrated in the second portion while the first portion consumes less power, resolving the contradiction between aliasing rejection and overall power consumption.
Solution Approach 2:
Different portions of the ADC circuit are assigned different operating characteristics: the first portion operates at the base sampling rate for power efficiency, while the second portion operates at a higher sampling rate specifically for aliasing rejection. This local differentiation of operational quality enables the system to achieve aliasing rejection without requiring the entire circuit to consume high power.
2Reliability
If conventional anti-aliasing filters are used to reject aliasing, then aliasing rejection is improved, but device complexity and cost increase
Solution Approach 1:
The aliasing rejection functionality is merged with the existing ADC circuit structure by having the second portion operate at a higher sampling rate. This integration eliminates the need for separate conventional anti-aliasing filters, reducing device complexity while maintaining aliasing rejection capability. The higher-rate portion works in conjunction with the base-rate portion to achieve the filtering effect inherently.
Solution Approach 2:
The second portion of the ADC circuit serves multiple functions: it performs the primary analog-to-digital conversion for its portion of the signal and simultaneously provides aliasing rejection for the overall system by operating at the higher sampling rate. This multi-functionality eliminates the need for dedicated anti-aliasing filter components, reducing overall device complexity.
3Speed
If a flash ADC architecture is used to achieve faster conversion speed, then conversion speed is improved, but power consumption and area increase exponentially
Solution Approach 1:
The ADC is segmented into a first portion (SAR ADC) that operates at the base sampling rate with lower power consumption and a second portion (flash ADC) that operates at a higher sampling rate for faster conversion of specific signal portions. This segmentation allows the system to achieve fast conversion where needed without requiring the entire ADC to consume the high power associated with full flash ADC operation.
Solution Approach 2:
Different ADC architectures are applied to different portions of the circuit based on local requirements: the first portion uses SAR ADC architecture for power efficiency at the base sampling rate, while the second portion uses flash ADC architecture for high-speed operation. This local optimization of architectural quality achieves fast conversion speed in the critical path while maintaining overall power efficiency.
Data Source
AI summary
Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.