ADC Array Path Selection for Nonvolatile Memory Sensing
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Solution Overview
Problem
Conventional DRAMs are volatile, requiring frequent refreshing due to capacitor leakage, and existing nonvolatile memory solutions face challenges in efficiently reading multi-level data stored in resistive memory cells.
Innovation Solution
A nonvolatile memory apparatus and semiconductor system that incorporates an ADC array to sense voltages from memory cells and a path selection unit to couple ADCs with memory subarrays or power supply voltage in different operation modes, enhancing data reading and power noise monitoring capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ADCs are used to sense sensing voltages from memory cells in a nonvolatile memory apparatus, then multi-level data reading capability is improved, but device complexity increases due to the need for additional ADC components and path selection units
Solution Approach 1:
The ADC array is designed to perform multiple functions: sensing sensing voltages from memory cells during normal read operations, and monitoring power supply voltages during power noise monitoring mode. The path selection unit enables the ADC array to be electrically coupled with either the memory cell array or the power supply voltage terminal depending on the operation mode, allowing one component to serve multiple purposes and reducing overall device complexity.
2Productivity
If the ADC array is electrically coupled with the memory cell array for normal read operations, then data reading efficiency is improved, but the ability to monitor power supply voltage noise is lost
Solution Approach 1:
The path selection unit dynamically reconfigures the electrical connections based on the operation mode. During normal read operations, it couples the ADC array with the memory cell array for efficient data reading. During power noise monitoring mode, it switches to couple the ADC array with the power supply voltage terminal. This dynamic switching capability allows the system to adapt between different functional requirements without compromising either data reading efficiency or power noise monitoring capability.
3Measurement precision
If high-performance ADCs are used to precisely sense sensing voltages from memory cells, then measurement precision is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The ADC array is designed to serve dual purposes: precise sensing of sensing voltages during normal operations and monitoring of power supply voltage during power noise monitoring mode. By making the ADC array multi-functional through the path selection unit, the system can use the same ADC components for both tasks, reducing the need for separate high-performance ADCs dedicated solely to memory cell sensing, thereby lowering manufacturing costs and device complexity while maintaining measurement precision when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient reading of multi-level data and power noise monitoring, increasing the utilization of ADCs and reducing the need for high-performance ADCs, thereby improving the reliability and efficiency of nonvolatile memory operations.
Implementation Method 1
a plurality of ADCs configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays
Implementation Method 2
a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode
Data Source
AI summary
A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode.