Two-Stage ADC Comparator with Auto-Zero Timing for Low Power

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Solution Overview

Problem

Analog-to-digital converters (ADCs) in image sensors face challenges in achieving improved resolution while maintaining low power consumption, as existing technologies often result in increased power consumption due to the need for enhanced signal processing capabilities.

Innovation Solution

The implementation of an analog-to-digital converting circuit with a two-stage comparator structure, utilizing auto-zero period optimization and output feedback, reduces power consumption by optimizing the auto-zero periods and incorporating a power-down mechanism for the second amplifier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the ADC processes more signals within the same time or provides improved resolution for each signal, then the resolution and signal processing capability are improved, but the power consumption increases

Engineering Contradiction:
ImproveresolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The ADC operation is divided into distinct time segments: an auto-zero period for offset compensation and a conversion period for signal conversion. During the auto-zero period, only the first amplifier operates to compensate for offsets, while the second amplifier is powered down. This temporal segmentation allows high-resolution conversion during the conversion period while minimizing power consumption during the auto-zero period, resolving the contradiction between improved resolution and reduced power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ADC employs periodic auto-zeroing operations where the first amplifier periodically compensates for offset voltages during dedicated auto-zero periods. This periodic action maintains high conversion precision by continuously correcting offsets without requiring the second amplifier to operate continuously, thereby achieving improved resolution while maintaining low power consumption during non-conversion phases.

Inventive Principle:
Principle #19Periodic action

2Measurement precision

If auto-zero periods are extended to improve offset compensation, then the conversion precision is improved, but the conversion speed decreases

Engineering Contradiction:
Improveconversion precisionVSAvoidconversion speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The auto-zero operation is segmented into a dedicated auto-zero period separate from the conversion period. During the auto-zero period, the first amplifier compensates for offsets with sufficient time to achieve high precision. During the conversion period, the second amplifier operates with the already-compensated first amplifier, ensuring fast conversion speed. This temporal segmentation resolves the contradiction by allocating full time for precision offset compensation without extending the overall conversion time.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4181398B1Analog-to-digital converting circuit using auto-zero period optimization and operation method thereof
Publication Date: 2025.12.10 SAMSUNG ELECTRONICS CO LTD
  • EP4181398B1 patent drawingFigure 1
  • EP4181398B1 patent drawingFigure 2
  • EP4181398B1 patent drawingFigure 3

AI summary

A circuit includes a first amplifier that first compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, second compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal in the first and second operation periods based on first and second comparison results; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, stops an operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which the first operation period starts, and generates a second output signal based on the first output signal in the first operation period and the second operation period.