CMOS Image Sensor ADC Power Reduction via Bias Control
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Solution Overview
Problem
CMOS image sensors require a differential comparator for noise reduction, but existing analog-to-digital converters with differential comparators consume high power due to continuous current consumption.
Innovation Solution
An analog-to-digital converter design that includes a comparator, latch, and bias control unit, where the comparator is turned on by a bias voltage and deactivated when the ramp voltage exceeds the analog voltage, reducing power consumption by uncoupling the bias voltage and using charge dissipation transistors to dissipate charge from bias transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a differential comparator is used for noise reduction, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by controlling the bias voltage to the differential comparator in a periodic manner - applying bias voltage during the integration period when comparison is needed, and removing it during other periods. This allows the comparator to operate only when required for analog-to-digital conversion, reducing continuous power consumption while maintaining measurement precision during active comparison periods
Solution Approach 2:
The patent implements dynamics by making the bias voltage state changeable - transitioning between applied and removed states based on the operational phase. The bias voltage is dynamically controlled to be applied during integration/comparison phases and removed during non-active phases, allowing the system to adapt power consumption to actual operational needs while preserving comparator functionality when required
2Measurement precision
If the comparator operates continuously for accurate voltage comparison, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The bias voltage is applied periodically during integration periods when voltage comparison is required and removed during non-active periods. This periodic application ensures accurate voltage comparison happens during critical measurement windows while eliminating continuous current consumption during idle periods, resolving the contradiction between continuous operation and power savings
3Reliability
If the bias voltage is continuously applied to the comparator, then reliability is improved, but power consumption increases
Solution Approach 1:
The bias voltage is applied in advance during the integration period before the actual comparison needs to occur. This preliminary application ensures the comparator is fully biased and ready for accurate comparison when the ramp voltage and analog signal are being compared, while allowing the bias to be removed afterward to save power, thus maintaining reliability during critical periods without continuous power consumption
Data Source
AI summary
An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.