Parallel ADC Comparator Biasing for CMOS Image Sensor Noise
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Solution Overview
Problem
In solid-state imaging devices, particularly CMOS image sensors, the bias voltage fluctuations due to noise on the common-bias line affect the performance of analog-to-digital converters when multiple converters operate in parallel, leading to errors and a striped pattern in image capture.
Innovation Solution
The implementation of a comparator with a first differential amplifier and a second single-ended amplifier, utilizing an auto-zero operation and self-bias circuit, along with a current compensation circuit, to stabilize the bias voltage and reduce noise, thereby minimizing fluctuations and improving image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple analog-to-digital converters operate in parallel using a common-bias circuit, then productivity increases, but bias voltage stability deteriorates due to noise on the common-bias line
Solution Approach 1:
The patent divides the common-bias circuit into individual separate bias circuits for each analog-to-digital converter. Each converter now has its own dedicated bias voltage supply, eliminating the shared common-bias line that caused noise coupling. This segmentation allows multiple converters to operate in parallel while maintaining bias voltage stability for each individual converter.
2Device complexity
If a common-bias circuit is used for multiple amplifiers, then device complexity is reduced, but measurement precision deteriorates due to bias voltage fluctuations
Solution Approach 1:
The patent segments the bias circuit configuration so that each amplifier within an analog-to-digital converter has its own dedicated bias voltage supply rather than sharing a common bias line. This eliminates noise-induced voltage fluctuations that would otherwise affect signal comparison accuracy, while maintaining reasonable circuit complexity through the modular converter structure.
3Ease of manufacture
If bias voltage is supplied through a common-bias line, then ease of manufacture is improved, but reliability deteriorates due to noise-induced voltage fluctuations
Solution Approach 1:
The patent implements separate bias voltage supplies for each analog-to-digital converter, eliminating the common-bias line architecture. While this increases circuit component count slightly, it dramatically improves reliability by preventing noise-induced voltage fluctuations from affecting converter operation. The modular nature of the separate bias circuits maintains ease of manufacture through standardized individual converter units.
Data Source
AI summary
It is an object of the present invention to provide a technique for reducing the variation of a bias voltage.An analog-to-digital converter comprises a comparator including a first amplifier and a second amplifier inputted one output of the first amplifier. The first amplifier is a differential type of amplifier, and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal which changes with a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto zero voltage based on the amplified voltage by an auto zero operation of the first amplifier and includes a self-bias circuit using the auto zero voltage as a bias voltage. The comparator is plural, the comparators are plurality which arranged in a row direction, and outputs a digital value based on an analog voltage inputted to the other input terminal in parallel operation.