Interleaved ADC Clock Skew Calibration with Binary Tree Auto-Correlators
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Solution Overview
Problem
Interleaved Analog-to-Digital Converters (ADCs) face challenges in achieving high sampling rates due to sampling pulse-width mismatches and component mismatches, leading to non-linearities and spurious tones that restrict dynamic range and are proportional to the analog input signal amplitude and frequency.
Innovation Solution
A calibration method using auto-correlators and Successive-Approximation-Register (SAR) delay elements introduces programmable delays to correct timing skews among multiple channels, minimizing sampling pulse-width and component mismatches through foreground and background calibration routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ADC channels are interleaved together to achieve higher sampling rates, then the sampling rate is improved, but timing skews and component mismatches among channels introduce spurious tones that restrict dynamic range
Solution Approach 1:
The patent applies preliminary action by performing calibration of timing skews and component mismatches before the interleaved ADC operates in its final mode. The calibration process adjusts delay elements in each channel to equalize timing parameters ahead of time, ensuring that when the high-speed interleaved operation begins, the channels are already synchronized and mismatch-corrected, thereby preventing spurious tones from degrading dynamic range
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay parameters of each ADC channel during calibration. The system measures timing skews and component mismatches, then modifies the delay element values (such as capacitor sizes in switched-capacitor delay circuits) to compensate for these variations. This parameter adjustment equalizes the timing and frequency response across all interleaved channels, reducing spurious tones while maintaining the high sampling rate
2Measurement precision
If sampling pulse width is increased to improve ADC accuracy, then measurement precision is improved, but pulse-width mismatches among channels introduce non-linearities and spurious tones
Solution Approach 1:
The patent applies local quality by allowing each ADC channel to have its own optimized sampling pulse width tailored to its specific characteristics. Instead of using a uniform pulse width for all channels, the system independently adjusts the pulse width for each channel based on its timing skew and component characteristics, thereby maximizing each channel's accuracy while maintaining overall synchronization through separate delay control
Solution Approach 2:
The patent applies dynamics by making the sampling pulse width adjustable and adaptive for each channel. The calibration process dynamically determines the optimal pulse width for each channel and configures the delay elements accordingly. This dynamic adjustment allows the system to optimize measurement precision for each channel while compensating for timing variations, thereby reducing spurious tones that would result from fixed uniform pulse widths
3Manufacturing precision
If calibration complexity is increased to reduce timing skews among channels, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the calibration process into separate, independent adjustments for each ADC channel. Instead of attempting to calibrate all channels simultaneously as a complex system, the method segments the calibration into individual channel measurements and adjustments. Each channel's delay elements are calibrated independently based on its specific timing characteristics, simplifying the overall calibration architecture while achieving precise timing equalization across all channels
Solution Approach 2:
The patent applies self-service by enabling each ADC channel to be self-calibrated through automated measurement and adjustment. The calibration system automatically measures timing skews and component mismatches for each channel and adjusts the delay elements without requiring manual intervention or complex external equipment. This self-calibrating approach reduces device complexity by eliminating the need for sophisticated external calibration apparatus while achieving high manufacturing precision in timing equalization
Data Source
AI summary
An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. An auto-correlator generates a sign of a correlation error for a pair of ADC digital outputs. SAR bits are tested with the correlation sign bit determining when to add or subtract SAR bits. First all pairs are calibrated in a first level of a binary tree of mux-correlators. Then skews between remote pairs and groups are calibrated in upper levels of the binary tree using auto-correlators with inputs muxed from groups of ADC outputs input to the binary tree of mux-correlators. The binary tree of mux-correlators can include bypasses for odd and non-binary values of N. Sampling clock and component timing skews are reduced to one LSB among both adjacent channels and remote channels.